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target/mips: Remove unreachable 32-bit code on 64-bit Loongson Ext 

Loongson fixed-point multiplies and divisions opcodes are
specific to 64-bit cores (Loongson-2 and Loongson-3 families).
Simplify by removing the 32-bit checks.

Reported-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20241026175349.84523-10-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2024-10-26 12:24:46 -03:00
parent ad6e1f194f
commit 74665884a5
1 changed files with 2 additions and 39 deletions
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41
target/mips/tcg/loong_translate.c
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@ -31,13 +31,6 @@ static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt,
TCGv t0, t1;
TCGLabel *l1, *l2, *l3;
if (is_double) {
if (TARGET_LONG_BITS != 64) {
return false;
}
check_mips_64(s);
}
if (rd == 0) {
/* Treat as NOP. */
return true;
@ -61,8 +54,7 @@ static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt,
tcg_gen_br(l3);
gen_set_label(l1);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double && TARGET_LONG_BITS == 64
? LLONG_MIN : INT_MIN, l2);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double ? LLONG_MIN : INT_MIN, l2);
tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
tcg_gen_mov_tl(cpu_gpr[rd], t0);
@ -93,13 +85,6 @@ static bool gen_lext_DIVU_G(DisasContext *s, int rd, int rs, int rt,
TCGv t0, t1;
TCGLabel *l1, *l2;
if (is_double) {
if (TARGET_LONG_BITS != 64) {
return false;
}
check_mips_64(s);
}
if (rd == 0) {
/* Treat as NOP. */
return true;
@ -147,13 +132,6 @@ static bool gen_lext_MOD_G(DisasContext *s, int rd, int rs, int rt,
TCGv t0, t1;
TCGLabel *l1, *l2, *l3;
if (is_double) {
if (TARGET_LONG_BITS != 64) {
return false;
}
check_mips_64(s);
}
if (rd == 0) {
/* Treat as NOP. */
return true;
@ -173,8 +151,7 @@ static bool gen_lext_MOD_G(DisasContext *s, int rd, int rs, int rt,
tcg_gen_ext32u_tl(t1, t1);
}
tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double && TARGET_LONG_BITS == 64
? LLONG_MIN : INT_MIN, l2);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double ? LLONG_MIN : INT_MIN, l2);
tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
gen_set_label(l1);
tcg_gen_movi_tl(cpu_gpr[rd], 0);
@ -205,13 +182,6 @@ static bool gen_lext_MODU_G(DisasContext *s, int rd, int rs, int rt,
TCGv t0, t1;
TCGLabel *l1, *l2;
if (is_double) {
if (TARGET_LONG_BITS != 64) {
return false;
}
check_mips_64(s);
}
if (rd == 0) {
/* Treat as NOP. */
return true;
@ -257,13 +227,6 @@ static bool gen_lext_MULT_G(DisasContext *s, int rd, int rs, int rt,
{
TCGv t0, t1;
if (is_double) {
if (TARGET_LONG_BITS != 64) {
return false;
}
check_mips_64(s);
}
if (rd == 0) {
/* Treat as NOP. */
return true;