mirror of https://github.com/xemu-project/xemu.git
Hexagon (target/hexagon) properly generate TB end for DISAS_NORETURN
When exiting a TB, generate all the code before returning from hexagon_tr_translate_packet so that nothing needs to be done in hexagon_tr_tb_stop. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-6-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -54,16 +54,40 @@ static const char * const hexagon_prednames[] = {
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"p0", "p1", "p2", "p3"
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"p0", "p1", "p2", "p3"
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};
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};
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void gen_exception(int excp)
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static void gen_exception_raw(int excp)
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{
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{
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TCGv_i32 helper_tmp = tcg_const_i32(excp);
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TCGv_i32 helper_tmp = tcg_const_i32(excp);
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gen_helper_raise_exception(cpu_env, helper_tmp);
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gen_helper_raise_exception(cpu_env, helper_tmp);
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tcg_temp_free_i32(helper_tmp);
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tcg_temp_free_i32(helper_tmp);
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}
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}
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void gen_exception_debug(void)
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static void gen_exec_counters(DisasContext *ctx)
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{
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{
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gen_exception(EXCP_DEBUG);
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tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_PKT_CNT],
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hex_gpr[HEX_REG_QEMU_PKT_CNT], ctx->num_packets);
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tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_INSN_CNT],
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hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns);
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}
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static void gen_end_tb(DisasContext *ctx)
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{
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gen_exec_counters(ctx);
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tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC);
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if (ctx->base.singlestep_enabled) {
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gen_exception_raw(EXCP_DEBUG);
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} else {
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tcg_gen_exit_tb(NULL, 0);
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}
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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static void gen_exception_end_tb(DisasContext *ctx, int excp)
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{
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gen_exec_counters(ctx);
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tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC);
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gen_exception_raw(excp);
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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}
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#if HEX_DEBUG
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#if HEX_DEBUG
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@ -225,8 +249,7 @@ static void gen_insn(CPUHexagonState *env, DisasContext *ctx,
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mark_implicit_writes(ctx, insn);
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mark_implicit_writes(ctx, insn);
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insn->generate(env, ctx, insn, pkt);
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insn->generate(env, ctx, insn, pkt);
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} else {
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} else {
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gen_exception(HEX_EXCP_INVALID_OPCODE);
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gen_exception_end_tb(ctx, HEX_EXCP_INVALID_OPCODE);
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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}
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}
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}
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@ -447,14 +470,6 @@ static void update_exec_counters(DisasContext *ctx, Packet *pkt)
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ctx->num_insns += num_real_insns;
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ctx->num_insns += num_real_insns;
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}
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}
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static void gen_exec_counters(DisasContext *ctx)
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{
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tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_PKT_CNT],
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hex_gpr[HEX_REG_QEMU_PKT_CNT], ctx->num_packets);
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tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_INSN_CNT],
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hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns);
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}
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static void gen_commit_packet(DisasContext *ctx, Packet *pkt)
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static void gen_commit_packet(DisasContext *ctx, Packet *pkt)
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{
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{
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gen_reg_writes(ctx);
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gen_reg_writes(ctx);
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@ -478,7 +493,7 @@ static void gen_commit_packet(DisasContext *ctx, Packet *pkt)
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#endif
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#endif
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if (pkt->pkt_has_cof) {
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if (pkt->pkt_has_cof) {
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ctx->base.is_jmp = DISAS_NORETURN;
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gen_end_tb(ctx);
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}
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}
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}
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}
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@ -491,8 +506,7 @@ static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx)
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nwords = read_packet_words(env, ctx, words);
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nwords = read_packet_words(env, ctx, words);
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if (!nwords) {
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if (!nwords) {
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gen_exception(HEX_EXCP_INVALID_PACKET);
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gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET);
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ctx->base.is_jmp = DISAS_NORETURN;
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return;
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return;
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}
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}
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@ -505,8 +519,7 @@ static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx)
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gen_commit_packet(ctx, &pkt);
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gen_commit_packet(ctx, &pkt);
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ctx->base.pc_next += pkt.encod_pkt_size_in_bytes;
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ctx->base.pc_next += pkt.encod_pkt_size_in_bytes;
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} else {
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} else {
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gen_exception(HEX_EXCP_INVALID_PACKET);
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gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET);
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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}
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}
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}
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@ -536,9 +549,7 @@ static bool hexagon_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
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{
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next);
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gen_exception_end_tb(ctx, EXCP_DEBUG);
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ctx->base.is_jmp = DISAS_NORETURN;
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gen_exception_debug();
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/*
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/*
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* The address covered by the breakpoint must be included in
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* The address covered by the breakpoint must be included in
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* [tb->pc, tb->pc + tb->size) in order to for it to be
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* [tb->pc, tb->pc + tb->size) in order to for it to be
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@ -601,19 +612,12 @@ static void hexagon_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
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gen_exec_counters(ctx);
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gen_exec_counters(ctx);
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tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next);
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tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next);
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if (ctx->base.singlestep_enabled) {
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if (ctx->base.singlestep_enabled) {
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gen_exception_debug();
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gen_exception_raw(EXCP_DEBUG);
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} else {
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} else {
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tcg_gen_exit_tb(NULL, 0);
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tcg_gen_exit_tb(NULL, 0);
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}
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}
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break;
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break;
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case DISAS_NORETURN:
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case DISAS_NORETURN:
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gen_exec_counters(ctx);
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tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC);
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if (ctx->base.singlestep_enabled) {
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gen_exception_debug();
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} else {
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tcg_gen_exit_tb(NULL, 0);
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}
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break;
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break;
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default:
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default:
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g_assert_not_reached();
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g_assert_not_reached();
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@ -86,8 +86,5 @@ extern TCGv hex_llsc_addr;
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extern TCGv hex_llsc_val;
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extern TCGv hex_llsc_val;
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extern TCGv_i64 hex_llsc_val_i64;
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extern TCGv_i64 hex_llsc_val_i64;
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void gen_exception(int excp);
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void gen_exception_debug(void);
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void process_store(DisasContext *ctx, Packet *pkt, int slot_num);
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void process_store(DisasContext *ctx, Packet *pkt, int slot_num);
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#endif
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#endif
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