mirror of https://github.com/xemu-project/xemu.git
target/riscv: Remove experimental prefix from "B" extension
This extension has now been ratified: https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be removed. Since this is now a ratified extension add it to the list of extensions included in the "max" CPU variant. Signed-off-by: Rob Bradford <rbradford@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
parent
6c9a344247
commit
73ef14b127
|
@ -1400,7 +1400,7 @@ static const MISAExtInfo misa_ext_info_arr[] = {
|
|||
MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
|
||||
MISA_EXT_INFO(RVV, "v", "Vector operations"),
|
||||
MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
|
||||
MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
|
||||
MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
|
||||
};
|
||||
|
||||
static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
|
||||
|
|
|
@ -1301,7 +1301,7 @@ static void riscv_init_max_cpu_extensions(Object *obj)
|
|||
const RISCVCPUMultiExtConfig *prop;
|
||||
|
||||
/* Enable RVG, RVJ and RVV that are disabled by default */
|
||||
riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
|
||||
riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
|
||||
|
||||
for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
|
||||
isa_ext_update_enabled(cpu, prop->offset, true);
|
||||
|
|
Loading…
Reference in New Issue