mirror of https://github.com/xemu-project/xemu.git
target/arm: Convert to CPUClass::tlb_fill
Cc: qemu-arm@nongnu.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
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e41c945297
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@ -2133,23 +2133,6 @@ static Property arm_cpu_properties[] = {
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DEFINE_PROP_END_OF_LIST()
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};
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#ifdef CONFIG_USER_ONLY
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static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
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int rw, int mmu_idx)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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env->exception.vaddress = address;
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if (rw == 2) {
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cs->exception_index = EXCP_PREFETCH_ABORT;
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} else {
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cs->exception_index = EXCP_DATA_ABORT;
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}
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return 1;
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}
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#endif
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static gchar *arm_gdb_arch_name(CPUState *cs)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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@ -2182,9 +2165,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
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cc->synchronize_from_tb = arm_cpu_synchronize_from_tb;
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cc->gdb_read_register = arm_cpu_gdb_read_register;
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cc->gdb_write_register = arm_cpu_gdb_write_register;
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#ifdef CONFIG_USER_ONLY
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cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
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#else
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#ifndef CONFIG_USER_ONLY
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cc->do_interrupt = arm_cpu_do_interrupt;
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cc->do_unaligned_access = arm_cpu_do_unaligned_access;
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cc->do_transaction_failed = arm_cpu_do_transaction_failed;
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@ -2209,6 +2190,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
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cc->disas_set_info = arm_disas_set_info;
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#ifdef CONFIG_TCG
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cc->tcg_initialize = arm_translate_init;
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cc->tlb_fill = arm_cpu_tlb_fill;
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#endif
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}
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@ -12596,43 +12596,6 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
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}
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}
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/* Walk the page table and (if the mapping exists) add the page
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* to the TLB. Return false on success, or true on failure. Populate
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* fsr with ARM DFSR/IFSR fault register format value on failure.
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*/
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bool arm_tlb_fill(CPUState *cs, vaddr address,
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MMUAccessType access_type, int mmu_idx,
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ARMMMUFaultInfo *fi)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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hwaddr phys_addr;
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target_ulong page_size;
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int prot;
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int ret;
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MemTxAttrs attrs = {};
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ret = get_phys_addr(env, address, access_type,
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core_to_arm_mmu_idx(env, mmu_idx), &phys_addr,
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&attrs, &prot, &page_size, fi, NULL);
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if (!ret) {
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/*
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* Map a single [sub]page. Regions smaller than our declared
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* target page size are handled specially, so for those we
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* pass in the exact addresses.
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*/
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if (page_size >= TARGET_PAGE_SIZE) {
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phys_addr &= TARGET_PAGE_MASK;
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address &= TARGET_PAGE_MASK;
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}
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tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
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prot, mmu_idx, page_size);
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return 0;
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}
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return ret;
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}
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hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
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MemTxAttrs *attrs)
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{
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@ -13111,6 +13074,67 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
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#endif
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bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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#ifdef CONFIG_USER_ONLY
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cpu->env.exception.vaddress = address;
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if (access_type == MMU_INST_FETCH) {
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cs->exception_index = EXCP_PREFETCH_ABORT;
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} else {
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cs->exception_index = EXCP_DATA_ABORT;
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}
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cpu_loop_exit_restore(cs, retaddr);
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#else
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hwaddr phys_addr;
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target_ulong page_size;
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int prot, ret;
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MemTxAttrs attrs = {};
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ARMMMUFaultInfo fi = {};
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/*
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* Walk the page table and (if the mapping exists) add the page
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* to the TLB. On success, return true. Otherwise, if probing,
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* return false. Otherwise populate fsr with ARM DFSR/IFSR fault
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* register format, and signal the fault.
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*/
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ret = get_phys_addr(&cpu->env, address, access_type,
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core_to_arm_mmu_idx(&cpu->env, mmu_idx),
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&phys_addr, &attrs, &prot, &page_size, &fi, NULL);
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if (likely(!ret)) {
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/*
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* Map a single [sub]page. Regions smaller than our declared
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* target page size are handled specially, so for those we
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* pass in the exact addresses.
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*/
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if (page_size >= TARGET_PAGE_SIZE) {
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phys_addr &= TARGET_PAGE_MASK;
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address &= TARGET_PAGE_MASK;
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}
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tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
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prot, mmu_idx, page_size);
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return true;
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} else if (probe) {
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return false;
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} else {
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/* now we have a real cpu fault */
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cpu_restore_state(cs, retaddr, true);
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arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi);
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}
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#endif
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}
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#ifndef CONFIG_USER_ONLY
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void tlb_fill(CPUState *cs, target_ulong addr, int size,
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MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
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{
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arm_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr);
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}
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#endif
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void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
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{
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/* Implement DC ZVA, which zeroes a fixed-length block of memory.
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@ -761,10 +761,12 @@ static inline bool arm_extabort_type(MemTxResult result)
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return result != MEMTX_DECODE_ERROR;
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}
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/* Do a page table walk and add page to TLB if possible */
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bool arm_tlb_fill(CPUState *cpu, vaddr address,
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MMUAccessType access_type, int mmu_idx,
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ARMMMUFaultInfo *fi);
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bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type,
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int mmu_idx, ARMMMUFaultInfo *fi) QEMU_NORETURN;
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/* Return true if the stage 1 translation regime is using LPAE format page
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* tables */
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@ -126,8 +126,8 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
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return syn;
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}
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static void deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type,
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int mmu_idx, ARMMMUFaultInfo *fi)
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void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type,
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int mmu_idx, ARMMMUFaultInfo *fi)
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{
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CPUARMState *env = &cpu->env;
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int target_el;
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@ -179,27 +179,6 @@ static void deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type,
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raise_exception(env, exc, syn, target_el);
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}
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/* try to fill the TLB and return an exception if error. If retaddr is
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* NULL, it means that the function was called in C code (i.e. not
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* from generated code or from helper.c)
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*/
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void tlb_fill(CPUState *cs, target_ulong addr, int size,
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MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
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{
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bool ret;
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ARMMMUFaultInfo fi = {};
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ret = arm_tlb_fill(cs, addr, access_type, mmu_idx, &fi);
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if (unlikely(ret)) {
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ARMCPU *cpu = ARM_CPU(cs);
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/* now we have a real cpu fault */
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cpu_restore_state(cs, retaddr, true);
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deliver_fault(cpu, addr, access_type, mmu_idx, &fi);
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}
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}
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/* Raise a data fault alignment exception for the specified virtual address */
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void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
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MMUAccessType access_type,
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@ -212,7 +191,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
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cpu_restore_state(cs, retaddr, true);
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fi.type = ARMFault_Alignment;
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deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi);
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arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi);
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}
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/* arm_cpu_do_transaction_failed: handle a memory system error response
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fi.ea = arm_extabort_type(response);
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fi.type = ARMFault_SyncExternal;
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deliver_fault(cpu, addr, access_type, mmu_idx, &fi);
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arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi);
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}
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#endif /* !defined(CONFIG_USER_ONLY) */
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