From 73123406f3bc455b3320fee08741e1d81b471e72 Mon Sep 17 00:00:00 2001 From: Song Gao Date: Thu, 14 Sep 2023 10:26:03 +0800 Subject: [PATCH] target/loongarch: Implement xvreplgr2vr This patch includes: - XVREPLGR2VR.{B/H/W/D}. Signed-off-by: Song Gao Reviewed-by: Richard Henderson Message-Id: <20230914022645.1151356-16-gaosong@loongson.cn> --- target/loongarch/disas.c | 10 +++++++++ target/loongarch/insn_trans/trans_vec.c.inc | 25 +++++++++++++++------ target/loongarch/insns.decode | 5 +++++ 3 files changed, 33 insertions(+), 7 deletions(-) diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c index d8b62ba532..c47f455ed0 100644 --- a/target/loongarch/disas.c +++ b/target/loongarch/disas.c @@ -1708,6 +1708,11 @@ static void output_vvv_x(DisasContext *ctx, arg_vvv * a, const char *mnemonic) output(ctx, mnemonic, "x%d, x%d, x%d", a->vd, a->vj, a->vk); } +static void output_vr_x(DisasContext *ctx, arg_vr *a, const char *mnemonic) +{ + output(ctx, mnemonic, "x%d, r%d", a->vd, a->rj); +} + INSN_LASX(xvadd_b, vvv) INSN_LASX(xvadd_h, vvv) INSN_LASX(xvadd_w, vvv) @@ -1718,3 +1723,8 @@ INSN_LASX(xvsub_h, vvv) INSN_LASX(xvsub_w, vvv) INSN_LASX(xvsub_d, vvv) INSN_LASX(xvsub_q, vvv) + +INSN_LASX(xvreplgr2vr_b, vr) +INSN_LASX(xvreplgr2vr_h, vr) +INSN_LASX(xvreplgr2vr_w, vr) +INSN_LASX(xvreplgr2vr_d, vr) diff --git a/target/loongarch/insn_trans/trans_vec.c.inc b/target/loongarch/insn_trans/trans_vec.c.inc index 3252e1d809..5001042870 100644 --- a/target/loongarch/insn_trans/trans_vec.c.inc +++ b/target/loongarch/insn_trans/trans_vec.c.inc @@ -4400,27 +4400,38 @@ static bool trans_vpickve2gr_du(DisasContext *ctx, arg_rv_i *a) return true; } -static bool gvec_dup(DisasContext *ctx, arg_vr *a, MemOp mop) +static bool gvec_dup_vl(DisasContext *ctx, arg_vr *a, + uint32_t oprsz, MemOp mop) { TCGv src = gpr_src(ctx, a->rj, EXT_NONE); - if (!avail_LSX(ctx)) { - return false; - } - - if (!check_vec(ctx, 16)) { + if (!check_vec(ctx, oprsz)) { return true; } tcg_gen_gvec_dup_i64(mop, vec_full_offset(a->vd), - 16, ctx->vl/8, src); + oprsz, ctx->vl/8, src); return true; } +static bool gvec_dup(DisasContext *ctx, arg_vr *a, MemOp mop) +{ + return gvec_dup_vl(ctx, a, 16, mop); +} + +static bool gvec_dupx(DisasContext *ctx, arg_vr *a, MemOp mop) +{ + return gvec_dup_vl(ctx, a, 32, mop); +} + TRANS(vreplgr2vr_b, LSX, gvec_dup, MO_8) TRANS(vreplgr2vr_h, LSX, gvec_dup, MO_16) TRANS(vreplgr2vr_w, LSX, gvec_dup, MO_32) TRANS(vreplgr2vr_d, LSX, gvec_dup, MO_64) +TRANS(xvreplgr2vr_b, LASX, gvec_dupx, MO_8) +TRANS(xvreplgr2vr_h, LASX, gvec_dupx, MO_16) +TRANS(xvreplgr2vr_w, LASX, gvec_dupx, MO_32) +TRANS(xvreplgr2vr_d, LASX, gvec_dupx, MO_64) static bool trans_vreplvei_b(DisasContext *ctx, arg_vv_i *a) { diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode index bcc18fb6c5..04bd238995 100644 --- a/target/loongarch/insns.decode +++ b/target/loongarch/insns.decode @@ -1310,3 +1310,8 @@ xvsub_h 0111 01000000 11001 ..... ..... ..... @vvv xvsub_w 0111 01000000 11010 ..... ..... ..... @vvv xvsub_d 0111 01000000 11011 ..... ..... ..... @vvv xvsub_q 0111 01010010 11011 ..... ..... ..... @vvv + +xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr +xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr +xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr +xvreplgr2vr_d 0111 01101001 11110 00011 ..... ..... @vr