mirror of https://github.com/xemu-project/xemu.git
pci: fix pci_device_reset
Clear interrupt disable bit on reset, according to PCI spec. Fix pci_device_reset() with 64bit BAR. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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parent
1ddda5cd36
commit
71ebd6dcf9
17
hw/pci.c
17
hw/pci.c
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@ -155,15 +155,24 @@ static void pci_device_reset(PCIDevice *dev)
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dev->irq_state = 0;
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dev->irq_state = 0;
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pci_update_irq_status(dev);
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pci_update_irq_status(dev);
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dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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/* Clear all writeable bits */
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PCI_COMMAND_MASTER);
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pci_set_word(dev->config + PCI_COMMAND,
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pci_get_word(dev->config + PCI_COMMAND) &
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~pci_get_word(dev->wmask + PCI_COMMAND));
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dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
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dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
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dev->config[PCI_INTERRUPT_LINE] = 0x0;
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dev->config[PCI_INTERRUPT_LINE] = 0x0;
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for (r = 0; r < PCI_NUM_REGIONS; ++r) {
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for (r = 0; r < PCI_NUM_REGIONS; ++r) {
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if (!dev->io_regions[r].size) {
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PCIIORegion *region = &dev->io_regions[r];
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if (!region->size) {
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continue;
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continue;
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}
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}
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pci_set_long(dev->config + pci_bar(dev, r), dev->io_regions[r].type);
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if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
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region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
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pci_set_quad(dev->config + pci_bar(dev, r), region->type);
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} else {
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pci_set_long(dev->config + pci_bar(dev, r), region->type);
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}
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}
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}
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pci_update_mappings(dev);
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pci_update_mappings(dev);
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}
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}
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