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target/sparc: Use tlb_set_page_full 

Pass CPUTLBEntryFull to get_physical_address instead
of a collection of pointers.

Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-02-22 14:31:40 -10:00
parent 968f305e08
commit 71b7794bbe
1 changed files with 54 additions and 67 deletions
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121
target/sparc/mmu_helper.c
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@ -64,10 +64,9 @@ static const int perm_table[2][8] = {
} }
}; };
static int get_physical_address(CPUSPARCState *env, hwaddr *physical, static int get_physical_address(CPUSPARCState *env, CPUTLBEntryFull *full,
int *prot, int *access_index, MemTxAttrs *attrs, int *access_index, target_ulong address,
target_ulong address, int rw, int mmu_idx, int rw, int mmu_idx)
target_ulong *page_size)
{ {
int access_perms = 0; int access_perms = 0;
hwaddr pde_ptr; hwaddr pde_ptr;
@ -80,20 +79,20 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
is_user = mmu_idx == MMU_USER_IDX; is_user = mmu_idx == MMU_USER_IDX;
if (mmu_idx == MMU_PHYS_IDX) { if (mmu_idx == MMU_PHYS_IDX) {
*page_size = TARGET_PAGE_SIZE; full->lg_page_size = TARGET_PAGE_BITS;
/* Boot mode: instruction fetches are taken from PROM */ /* Boot mode: instruction fetches are taken from PROM */
if (rw == 2 && (env->mmuregs[0] & env->def.mmu_bm)) { if (rw == 2 && (env->mmuregs[0] & env->def.mmu_bm)) {
*physical = env->prom_addr | (address & 0x7ffffULL); full->phys_addr = env->prom_addr | (address & 0x7ffffULL);
*prot = PAGE_READ | PAGE_EXEC; full->prot = PAGE_READ | PAGE_EXEC;
return 0; return 0;
} }
*physical = address; full->phys_addr = address;
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; full->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return 0; return 0;
} }
*access_index = ((rw & 1) << 2) | (rw & 2) | (is_user ? 0 : 1); *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user ? 0 : 1);
*physical = 0xffffffffffff0000ULL; full->phys_addr = 0xffffffffffff0000ULL;
/* SPARC reference MMU table walk: Context table->L1->L2->PTE */ /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
/* Context base + context number */ /* Context base + context number */
@ -157,16 +156,17 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
case 2: /* L3 PTE */ case 2: /* L3 PTE */
page_offset = 0; page_offset = 0;
} }
*page_size = TARGET_PAGE_SIZE; full->lg_page_size = TARGET_PAGE_BITS;
break; break;
case 2: /* L2 PTE */ case 2: /* L2 PTE */
page_offset = address & 0x3f000; page_offset = address & 0x3f000;
*page_size = 0x40000; full->lg_page_size = 18;
} }
break; break;
case 2: /* L1 PTE */ case 2: /* L1 PTE */
page_offset = address & 0xfff000; page_offset = address & 0xfff000;
*page_size = 0x1000000; full->lg_page_size = 24;
break;
} }
} }
@ -188,16 +188,16 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
} }
/* the page can be put in the TLB */ /* the page can be put in the TLB */
*prot = perm_table[is_user][access_perms]; full->prot = perm_table[is_user][access_perms];
if (!(pde & PG_MODIFIED_MASK)) { if (!(pde & PG_MODIFIED_MASK)) {
/* only set write access if already dirty... otherwise wait /* only set write access if already dirty... otherwise wait
for dirty access */ for dirty access */
*prot &= ~PAGE_WRITE; full->prot &= ~PAGE_WRITE;
} }
/* Even if large ptes, we map only one 4KB page in the cache to /* Even if large ptes, we map only one 4KB page in the cache to
avoid filling it too fast */ avoid filling it too fast */
*physical = ((hwaddr)(pde & PTE_ADDR_MASK) << 4) + page_offset; full->phys_addr = ((hwaddr)(pde & PTE_ADDR_MASK) << 4) + page_offset;
return error_code; return error_code;
} }
@ -208,11 +208,9 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
{ {
SPARCCPU *cpu = SPARC_CPU(cs); SPARCCPU *cpu = SPARC_CPU(cs);
CPUSPARCState *env = &cpu->env; CPUSPARCState *env = &cpu->env;
hwaddr paddr; CPUTLBEntryFull full = {};
target_ulong vaddr; target_ulong vaddr;
target_ulong page_size; int error_code = 0, access_index;
int error_code = 0, prot, access_index;
MemTxAttrs attrs = {};
/* /*
* TODO: If we ever need tlb_vaddr_to_host for this target, * TODO: If we ever need tlb_vaddr_to_host for this target,
@ -223,16 +221,15 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
assert(!probe); assert(!probe);
address &= TARGET_PAGE_MASK; address &= TARGET_PAGE_MASK;
error_code = get_physical_address(env, &paddr, &prot, &access_index, &attrs, error_code = get_physical_address(env, &full, &access_index,
address, access_type, address, access_type, mmu_idx);
mmu_idx, &page_size);
vaddr = address; vaddr = address;
if (likely(error_code == 0)) { if (likely(error_code == 0)) {
qemu_log_mask(CPU_LOG_MMU, qemu_log_mask(CPU_LOG_MMU,
"Translate at %" VADDR_PRIx " -> " "Translate at %" VADDR_PRIx " -> "
HWADDR_FMT_plx ", vaddr " TARGET_FMT_lx "\n", HWADDR_FMT_plx ", vaddr " TARGET_FMT_lx "\n",
address, paddr, vaddr); address, full.phys_addr, vaddr);
tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); tlb_set_page_full(cs, mmu_idx, vaddr, &full);
return true; return true;
} }
@ -247,8 +244,8 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
permissions. If no mapping is available, redirect accesses to permissions. If no mapping is available, redirect accesses to
neverland. Fake/overridden mappings will be flushed when neverland. Fake/overridden mappings will be flushed when
switching to normal mode. */ switching to normal mode. */
prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; full.prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE); tlb_set_page_full(cs, mmu_idx, vaddr, &full);
return true; return true;
} else { } else {
if (access_type == MMU_INST_FETCH) { if (access_type == MMU_INST_FETCH) {
@ -545,8 +542,7 @@ static uint64_t build_sfsr(CPUSPARCState *env, int mmu_idx, int rw)
return sfsr; return sfsr;
} }
static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, static int get_physical_address_data(CPUSPARCState *env, CPUTLBEntryFull *full,
int *prot, MemTxAttrs *attrs,
target_ulong address, int rw, int mmu_idx) target_ulong address, int rw, int mmu_idx)
{ {
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
@ -579,11 +575,12 @@ static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical,
for (i = 0; i < 64; i++) { for (i = 0; i < 64; i++) {
/* ctx match, vaddr match, valid? */ /* ctx match, vaddr match, valid? */
if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical)) { if (ultrasparc_tag_match(&env->dtlb[i], address, context,
&full->phys_addr)) {
int do_fault = 0; int do_fault = 0;
if (TTE_IS_IE(env->dtlb[i].tte)) { if (TTE_IS_IE(env->dtlb[i].tte)) {
attrs->byte_swap = true; full->attrs.byte_swap = true;
} }
/* access ok? */ /* access ok? */
@ -616,9 +613,9 @@ static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical,
} }
if (!do_fault) { if (!do_fault) {
*prot = PAGE_READ; full->prot = PAGE_READ;
if (TTE_IS_W_OK(env->dtlb[i].tte)) { if (TTE_IS_W_OK(env->dtlb[i].tte)) {
*prot |= PAGE_WRITE; full->prot |= PAGE_WRITE;
} }
TTE_SET_USED(env->dtlb[i].tte); TTE_SET_USED(env->dtlb[i].tte);
@ -645,8 +642,7 @@ static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical,
return 1; return 1;
} }
static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical, static int get_physical_address_code(CPUSPARCState *env, CPUTLBEntryFull *full,
int *prot, MemTxAttrs *attrs,
target_ulong address, int mmu_idx) target_ulong address, int mmu_idx)
{ {
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
@ -681,7 +677,7 @@ static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical,
for (i = 0; i < 64; i++) { for (i = 0; i < 64; i++) {
/* ctx match, vaddr match, valid? */ /* ctx match, vaddr match, valid? */
if (ultrasparc_tag_match(&env->itlb[i], if (ultrasparc_tag_match(&env->itlb[i],
address, context, physical)) { address, context, &full->phys_addr)) {
/* access ok? */ /* access ok? */
if (TTE_IS_PRIV(env->itlb[i].tte) && is_user) { if (TTE_IS_PRIV(env->itlb[i].tte) && is_user) {
/* Fault status register */ /* Fault status register */
@ -708,7 +704,7 @@ static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical,
return 1; return 1;
} }
*prot = PAGE_EXEC; full->prot = PAGE_EXEC;
TTE_SET_USED(env->itlb[i].tte); TTE_SET_USED(env->itlb[i].tte);
return 0; return 0;
} }
@ -722,14 +718,13 @@ static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical,
return 1; return 1;
} }
static int get_physical_address(CPUSPARCState *env, hwaddr *physical, static int get_physical_address(CPUSPARCState *env, CPUTLBEntryFull *full,
int *prot, int *access_index, MemTxAttrs *attrs, int *access_index, target_ulong address,
target_ulong address, int rw, int mmu_idx, int rw, int mmu_idx)
target_ulong *page_size)
{ {
/* ??? We treat everything as a small page, then explicitly flush /* ??? We treat everything as a small page, then explicitly flush
everything when an entry is evicted. */ everything when an entry is evicted. */
*page_size = TARGET_PAGE_SIZE; full->lg_page_size = TARGET_PAGE_BITS;
/* safety net to catch wrong softmmu index use from dynamic code */ /* safety net to catch wrong softmmu index use from dynamic code */
if (env->tl > 0 && mmu_idx != MMU_NUCLEUS_IDX) { if (env->tl > 0 && mmu_idx != MMU_NUCLEUS_IDX) {
@ -747,17 +742,15 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
} }
if (mmu_idx == MMU_PHYS_IDX) { if (mmu_idx == MMU_PHYS_IDX) {
*physical = ultrasparc_truncate_physical(address); full->phys_addr = ultrasparc_truncate_physical(address);
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; full->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return 0; return 0;
} }
if (rw == 2) { if (rw == 2) {
return get_physical_address_code(env, physical, prot, attrs, address, return get_physical_address_code(env, full, address, mmu_idx);
mmu_idx);
} else { } else {
return get_physical_address_data(env, physical, prot, attrs, address, return get_physical_address_data(env, full, address, rw, mmu_idx);
rw, mmu_idx);
} }
} }
@ -768,25 +761,17 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
{ {
SPARCCPU *cpu = SPARC_CPU(cs); SPARCCPU *cpu = SPARC_CPU(cs);
CPUSPARCState *env = &cpu->env; CPUSPARCState *env = &cpu->env;
target_ulong vaddr; CPUTLBEntryFull full = {};
hwaddr paddr; int error_code = 0, access_index;
target_ulong page_size;
MemTxAttrs attrs = {};
int error_code = 0, prot, access_index;
address &= TARGET_PAGE_MASK; address &= TARGET_PAGE_MASK;
error_code = get_physical_address(env, &paddr, &prot, &access_index, &attrs, error_code = get_physical_address(env, &full, &access_index,
address, access_type, address, access_type, mmu_idx);
mmu_idx, &page_size);
if (likely(error_code == 0)) { if (likely(error_code == 0)) {
vaddr = address; trace_mmu_helper_mmu_fault(address, full.phys_addr, mmu_idx, env->tl,
trace_mmu_helper_mmu_fault(address, paddr, mmu_idx, env->tl,
env->dmmu.mmu_primary_context, env->dmmu.mmu_primary_context,
env->dmmu.mmu_secondary_context); env->dmmu.mmu_secondary_context);
tlb_set_page_full(cs, mmu_idx, address, &full);
tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, prot, mmu_idx,
page_size);
return true; return true;
} }
if (probe) { if (probe) {
@ -888,12 +873,14 @@ void dump_mmu(CPUSPARCState *env)
static int cpu_sparc_get_phys_page(CPUSPARCState *env, hwaddr *phys, static int cpu_sparc_get_phys_page(CPUSPARCState *env, hwaddr *phys,
target_ulong addr, int rw, int mmu_idx) target_ulong addr, int rw, int mmu_idx)
{ {
target_ulong page_size; CPUTLBEntryFull full = {};
int prot, access_index; int access_index, ret;
MemTxAttrs attrs = {};
return get_physical_address(env, phys, &prot, &access_index, &attrs, addr, ret = get_physical_address(env, &full, &access_index, addr, rw, mmu_idx);
rw, mmu_idx, &page_size); if (ret == 0) {
*phys = full.phys_addr;
}
return ret;
} }
#if defined(TARGET_SPARC64) #if defined(TARGET_SPARC64)