mirror of https://github.com/xemu-project/xemu.git
ppc patch queue for 2023-08-04:
This queue contains target/ppc register and VRMA fixes for 8.1. pegasos2 fixes are also included. -----BEGIN PGP SIGNATURE----- iIwEABYKADQWIQQX6/+ZI9AYAK8oOBk82cqW3gMxZAUCZM0YohYcZGFuaWVsaGI0 MTNAZ21haWwuY29tAAoJEDzZypbeAzFkuqAA/0QrRC8agLbSw1b8pN7bR9Yweqk8 VKFotbyAH4QKO42KAP9GNeHU8iUcKk4l9eWip75mvwUsrLP/8INFWNGv1t76AQ== =5m4V -----END PGP SIGNATURE----- Merge tag 'pull-ppc-20230804' of https://gitlab.com/danielhb/qemu into staging ppc patch queue for 2023-08-04: This queue contains target/ppc register and VRMA fixes for 8.1. pegasos2 fixes are also included. # -----BEGIN PGP SIGNATURE----- # # iIwEABYKADQWIQQX6/+ZI9AYAK8oOBk82cqW3gMxZAUCZM0YohYcZGFuaWVsaGI0 # MTNAZ21haWwuY29tAAoJEDzZypbeAzFkuqAA/0QrRC8agLbSw1b8pN7bR9Yweqk8 # VKFotbyAH4QKO42KAP9GNeHU8iUcKk4l9eWip75mvwUsrLP/8INFWNGv1t76AQ== # =5m4V # -----END PGP SIGNATURE----- # gpg: Signature made Fri 04 Aug 2023 08:26:26 AM PDT # gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164 # gpg: issuer "danielhb413@gmail.com" # gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164 * tag 'pull-ppc-20230804' of https://gitlab.com/danielhb/qemu: target/ppc: Fix VRMA page size for ISA v3.0 target/ppc: Fix pending HDEC when entering PM state target/ppc: Implement ASDR register for ISA v3.0 for HPT ppc/pegasos2: Fix reg property of 64 bit BARs in device tree ppc/pegasos2: Fix naming of device tree nodes ppc/pegasos2: Fix reg property of ROM BARs ppc/pegasos2: Fix reset state of USB functions Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
commit
71934cf6bf
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@ -324,9 +324,13 @@ static void pegasos2_machine_reset(MachineState *machine, ShutdownCause reason)
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pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 2) << 8) |
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PCI_INTERRUPT_LINE, 2, 0x409);
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pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 2) << 8) |
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PCI_COMMAND, 2, 0x7);
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pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 3) << 8) |
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PCI_INTERRUPT_LINE, 2, 0x409);
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pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 3) << 8) |
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PCI_COMMAND, 2, 0x7);
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pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
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PCI_INTERRUPT_LINE, 2, 0x9);
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@ -735,6 +739,13 @@ static void add_pci_device(PCIBus *bus, PCIDevice *d, void *opaque)
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pci_get_word(&d->config[PCI_VENDOR_ID]),
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pci_get_word(&d->config[PCI_DEVICE_ID]));
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if (pci_get_word(&d->config[PCI_CLASS_DEVICE]) ==
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PCI_CLASS_NETWORK_ETHERNET) {
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name = "ethernet";
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} else if (pci_get_word(&d->config[PCI_CLASS_DEVICE]) >> 8 ==
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PCI_BASE_CLASS_DISPLAY) {
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name = "display";
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}
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for (i = 0; device_map[i].id; i++) {
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if (!strcmp(pn, device_map[i].id)) {
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name = device_map[i].name;
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@ -762,11 +773,19 @@ static void add_pci_device(PCIBus *bus, PCIDevice *d, void *opaque)
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if (!d->io_regions[i].size) {
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continue;
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}
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cells[j] = cpu_to_be32(d->devfn << 8 | (PCI_BASE_ADDRESS_0 + i * 4));
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cells[j] = PCI_BASE_ADDRESS_0 + i * 4;
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if (cells[j] == 0x28) {
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cells[j] = 0x30;
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}
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cells[j] = cpu_to_be32(d->devfn << 8 | cells[j]);
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if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) {
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cells[j] |= cpu_to_be32(1 << 24);
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} else {
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cells[j] |= cpu_to_be32(2 << 24);
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if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
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cells[j] |= cpu_to_be32(3 << 24);
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} else {
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cells[j] |= cpu_to_be32(2 << 24);
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}
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if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
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cells[j] |= cpu_to_be32(4 << 28);
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}
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@ -921,6 +940,7 @@ static void *build_fdt(MachineState *machine, int *fdt_size)
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qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-display-device", 0);
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qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-size", 20);
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qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-version", 1);
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qemu_fdt_setprop_string(fdt, "/rtas", "name", "rtas");
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/* cpus */
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qemu_fdt_add_subnode(fdt, "/cpus");
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@ -2685,6 +2685,12 @@ void helper_pminsn(CPUPPCState *env, uint32_t insn)
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env->resume_as_sreset = (insn != PPC_PM_STOP) ||
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(env->spr[SPR_PSSCR] & PSSCR_EC);
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/* HDECR is not to wake from PM state, it may have already fired */
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if (env->resume_as_sreset) {
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PowerPCCPU *cpu = env_archcpu(env);
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ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 0);
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}
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ppc_maybe_interrupt(env);
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}
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#endif /* defined(TARGET_PPC64) */
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@ -770,7 +770,8 @@ static bool ppc_hash64_use_vrma(CPUPPCState *env)
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}
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}
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static void ppc_hash64_set_isi(CPUState *cs, int mmu_idx, uint64_t error_code)
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static void ppc_hash64_set_isi(CPUState *cs, int mmu_idx, uint64_t slb_vsid,
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uint64_t error_code)
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{
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CPUPPCState *env = &POWERPC_CPU(cs)->env;
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bool vpm;
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@ -782,13 +783,15 @@ static void ppc_hash64_set_isi(CPUState *cs, int mmu_idx, uint64_t error_code)
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}
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if (vpm && !mmuidx_hv(mmu_idx)) {
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cs->exception_index = POWERPC_EXCP_HISI;
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env->spr[SPR_ASDR] = slb_vsid;
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} else {
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cs->exception_index = POWERPC_EXCP_ISI;
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}
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env->error_code = error_code;
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}
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static void ppc_hash64_set_dsi(CPUState *cs, int mmu_idx, uint64_t dar, uint64_t dsisr)
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static void ppc_hash64_set_dsi(CPUState *cs, int mmu_idx, uint64_t slb_vsid,
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uint64_t dar, uint64_t dsisr)
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{
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CPUPPCState *env = &POWERPC_CPU(cs)->env;
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bool vpm;
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@ -802,6 +805,7 @@ static void ppc_hash64_set_dsi(CPUState *cs, int mmu_idx, uint64_t dar, uint64_t
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cs->exception_index = POWERPC_EXCP_HDSI;
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env->spr[SPR_HDAR] = dar;
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env->spr[SPR_HDSISR] = dsisr;
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env->spr[SPR_ASDR] = slb_vsid;
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} else {
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cs->exception_index = POWERPC_EXCP_DSI;
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env->spr[SPR_DAR] = dar;
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@ -870,12 +874,46 @@ static target_ulong rmls_limit(PowerPCCPU *cpu)
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return rma_sizes[rmls];
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}
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static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *slb)
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/* Return the LLP in SLB_VSID format */
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static uint64_t get_vrma_llp(PowerPCCPU *cpu)
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{
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CPUPPCState *env = &cpu->env;
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target_ulong lpcr = env->spr[SPR_LPCR];
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uint32_t vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT;
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target_ulong vsid = SLB_VSID_VRMA | ((vrmasd << 4) & SLB_VSID_LLP_MASK);
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uint64_t llp;
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if (env->mmu_model == POWERPC_MMU_3_00) {
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ppc_v3_pate_t pate;
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uint64_t ps, l, lp;
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/*
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* ISA v3.0 removes the LPCR[VRMASD] field and puts the VRMA base
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* page size (L||LP equivalent) in the PS field in the HPT partition
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* table entry.
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*/
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if (!ppc64_v3_get_pate(cpu, cpu->env.spr[SPR_LPIDR], &pate)) {
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error_report("Bad VRMA with no partition table entry");
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return 0;
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}
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ps = PATE0_GET_PS(pate.dw0);
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/* PS has L||LP in 3 consecutive bits, put them into SLB LLP format */
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l = (ps >> 2) & 0x1;
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lp = ps & 0x3;
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llp = (l << SLB_VSID_L_SHIFT) | (lp << SLB_VSID_LP_SHIFT);
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} else {
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uint64_t lpcr = env->spr[SPR_LPCR];
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target_ulong vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT;
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/* VRMASD LLP matches SLB format, just shift and mask it */
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llp = (vrmasd << SLB_VSID_LP_SHIFT) & SLB_VSID_LLP_MASK;
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}
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return llp;
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}
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static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *slb)
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{
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uint64_t llp = get_vrma_llp(cpu);
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target_ulong vsid = SLB_VSID_VRMA | llp;
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int i;
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for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
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@ -893,8 +931,7 @@ static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *slb)
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}
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}
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error_report("Bad page size encoding in LPCR[VRMASD]; LPCR=0x"
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TARGET_FMT_lx, lpcr);
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error_report("Bad VRMA page size encoding 0x" TARGET_FMT_lx, llp);
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return -1;
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}
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@ -963,13 +1000,13 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
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}
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switch (access_type) {
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case MMU_INST_FETCH:
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ppc_hash64_set_isi(cs, mmu_idx, SRR1_PROTFAULT);
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ppc_hash64_set_isi(cs, mmu_idx, 0, SRR1_PROTFAULT);
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break;
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case MMU_DATA_LOAD:
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ppc_hash64_set_dsi(cs, mmu_idx, eaddr, DSISR_PROTFAULT);
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ppc_hash64_set_dsi(cs, mmu_idx, 0, eaddr, DSISR_PROTFAULT);
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break;
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case MMU_DATA_STORE:
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ppc_hash64_set_dsi(cs, mmu_idx, eaddr,
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ppc_hash64_set_dsi(cs, mmu_idx, 0, eaddr,
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DSISR_PROTFAULT | DSISR_ISSTORE);
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break;
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default:
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@ -1022,7 +1059,7 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
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/* 3. Check for segment level no-execute violation */
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if (access_type == MMU_INST_FETCH && (slb->vsid & SLB_VSID_N)) {
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if (guest_visible) {
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ppc_hash64_set_isi(cs, mmu_idx, SRR1_NOEXEC_GUARD);
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ppc_hash64_set_isi(cs, mmu_idx, slb->vsid, SRR1_NOEXEC_GUARD);
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}
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return false;
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}
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@ -1035,13 +1072,14 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
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}
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switch (access_type) {
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case MMU_INST_FETCH:
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ppc_hash64_set_isi(cs, mmu_idx, SRR1_NOPTE);
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ppc_hash64_set_isi(cs, mmu_idx, slb->vsid, SRR1_NOPTE);
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break;
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case MMU_DATA_LOAD:
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ppc_hash64_set_dsi(cs, mmu_idx, eaddr, DSISR_NOPTE);
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ppc_hash64_set_dsi(cs, mmu_idx, slb->vsid, eaddr, DSISR_NOPTE);
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break;
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case MMU_DATA_STORE:
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ppc_hash64_set_dsi(cs, mmu_idx, eaddr, DSISR_NOPTE | DSISR_ISSTORE);
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ppc_hash64_set_dsi(cs, mmu_idx, slb->vsid, eaddr,
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DSISR_NOPTE | DSISR_ISSTORE);
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break;
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default:
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g_assert_not_reached();
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@ -1075,7 +1113,7 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
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if (PAGE_EXEC & ~amr_prot) {
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srr1 |= SRR1_IAMR; /* Access violates virt pg class key prot */
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}
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ppc_hash64_set_isi(cs, mmu_idx, srr1);
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ppc_hash64_set_isi(cs, mmu_idx, slb->vsid, srr1);
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} else {
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int dsisr = 0;
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if (need_prot & ~pp_prot) {
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@ -1087,7 +1125,7 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
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if (need_prot & ~amr_prot) {
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dsisr |= DSISR_AMR;
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}
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ppc_hash64_set_dsi(cs, mmu_idx, eaddr, dsisr);
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ppc_hash64_set_dsi(cs, mmu_idx, slb->vsid, eaddr, dsisr);
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}
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return false;
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}
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@ -41,8 +41,10 @@ void ppc_hash64_finalize(PowerPCCPU *cpu);
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#define SLB_VSID_KP 0x0000000000000400ULL
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#define SLB_VSID_N 0x0000000000000200ULL /* no-execute */
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#define SLB_VSID_L 0x0000000000000100ULL
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#define SLB_VSID_L_SHIFT PPC_BIT_NR(55)
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#define SLB_VSID_C 0x0000000000000080ULL /* class */
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#define SLB_VSID_LP 0x0000000000000030ULL
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#define SLB_VSID_LP_SHIFT PPC_BIT_NR(59)
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#define SLB_VSID_ATTR 0x0000000000000FFFULL
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#define SLB_VSID_LLP_MASK (SLB_VSID_L | SLB_VSID_LP)
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#define SLB_VSID_4K 0x0000000000000000ULL
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@ -58,6 +60,9 @@ void ppc_hash64_finalize(PowerPCCPU *cpu);
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#define SDR_64_HTABSIZE 0x000000000000001FULL
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#define PATE0_HTABORG 0x0FFFFFFFFFFC0000ULL
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#define PATE0_PS PPC_BITMASK(56, 58)
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#define PATE0_GET_PS(dw0) (((dw0) & PATE0_PS) >> PPC_BIT_NR(58))
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#define HPTES_PER_GROUP 8
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#define HASH_PTE_SIZE_64 16
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#define HASH_PTEG_SIZE_64 (HASH_PTE_SIZE_64 * HPTES_PER_GROUP)
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