mirror of https://github.com/xemu-project/xemu.git
hw/arm_sysctl: Handle SYS_CFGCTRL in a more structured way
The SYS_CFGCTRL register consists of separate fields for DCC, function, site, position and device, as well as a read/write bit. Refactor the code handling SYS_CFGCTRL writes to make it easier to add support for functions like SYS_CFG_OSC which support multiple device fields. We also pull the handling out into its own function for clarity, as there are potentially a lot of implementable subfunctions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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cdef10bb93
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7153832335
143
hw/arm_sysctl.c
143
hw/arm_sysctl.c
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@ -9,6 +9,7 @@
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#include "hw/hw.h"
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#include "qemu/timer.h"
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#include "qemu/bitops.h"
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#include "hw/sysbus.h"
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#include "hw/primecell.h"
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#include "sysemu/sysemu.h"
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@ -191,6 +192,110 @@ static uint64_t arm_sysctl_read(void *opaque, hwaddr offset,
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}
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}
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/* SYS_CFGCTRL functions */
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#define SYS_CFG_OSC 1
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#define SYS_CFG_VOLT 2
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#define SYS_CFG_AMP 3
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#define SYS_CFG_TEMP 4
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#define SYS_CFG_RESET 5
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#define SYS_CFG_SCC 6
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#define SYS_CFG_MUXFPGA 7
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#define SYS_CFG_SHUTDOWN 8
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#define SYS_CFG_REBOOT 9
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#define SYS_CFG_DVIMODE 11
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#define SYS_CFG_POWER 12
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#define SYS_CFG_ENERGY 13
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/* SYS_CFGCTRL site field values */
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#define SYS_CFG_SITE_MB 0
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#define SYS_CFG_SITE_DB1 1
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#define SYS_CFG_SITE_DB2 2
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/**
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* vexpress_cfgctrl_read:
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* @s: arm_sysctl_state pointer
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* @dcc, @function, @site, @position, @device: split out values from
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* SYS_CFGCTRL register
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* @val: pointer to where to put the read data on success
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*
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* Handle a VExpress SYS_CFGCTRL register read. On success, return true and
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* write the read value to *val. On failure, return false (and val may
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* or may not be written to).
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*/
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static bool vexpress_cfgctrl_read(arm_sysctl_state *s, unsigned int dcc,
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unsigned int function, unsigned int site,
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unsigned int position, unsigned int device,
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uint32_t *val)
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{
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/* We don't support anything other than DCC 0, board stack position 0
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* or sites other than motherboard/daughterboard:
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*/
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if (dcc != 0 || position != 0 ||
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(site != SYS_CFG_SITE_MB && site != SYS_CFG_SITE_DB1)) {
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goto cfgctrl_unimp;
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}
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switch (function) {
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default:
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break;
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}
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cfgctrl_unimp:
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qemu_log_mask(LOG_UNIMP,
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"arm_sysctl: Unimplemented SYS_CFGCTRL read of function "
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"0x%x DCC 0x%x site 0x%x position 0x%x device 0x%x\n",
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function, dcc, site, position, device);
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return false;
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}
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/**
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* vexpress_cfgctrl_write:
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* @s: arm_sysctl_state pointer
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* @dcc, @function, @site, @position, @device: split out values from
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* SYS_CFGCTRL register
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* @val: data to write
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*
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* Handle a VExpress SYS_CFGCTRL register write. On success, return true.
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* On failure, return false.
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*/
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static bool vexpress_cfgctrl_write(arm_sysctl_state *s, unsigned int dcc,
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unsigned int function, unsigned int site,
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unsigned int position, unsigned int device,
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uint32_t val)
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{
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/* We don't support anything other than DCC 0, board stack position 0
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* or sites other than motherboard/daughterboard:
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*/
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if (dcc != 0 || position != 0 ||
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(site != SYS_CFG_SITE_MB && site != SYS_CFG_SITE_DB1)) {
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goto cfgctrl_unimp;
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}
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switch (function) {
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case SYS_CFG_SHUTDOWN:
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if (site == SYS_CFG_SITE_MB && device == 0) {
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qemu_system_shutdown_request();
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return true;
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}
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break;
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case SYS_CFG_REBOOT:
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if (site == SYS_CFG_SITE_MB && device == 0) {
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qemu_system_reset_request();
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return true;
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}
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break;
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default:
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break;
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}
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cfgctrl_unimp:
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qemu_log_mask(LOG_UNIMP,
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"arm_sysctl: Unimplemented SYS_CFGCTRL write of function "
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"0x%x DCC 0x%x site 0x%x position 0x%x device 0x%x\n",
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function, dcc, site, position, device);
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return false;
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}
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static void arm_sysctl_write(void *opaque, hwaddr offset,
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uint64_t val, unsigned size)
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{
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@ -322,17 +427,33 @@ static void arm_sysctl_write(void *opaque, hwaddr offset,
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if (board_id(s) != BOARD_ID_VEXPRESS) {
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goto bad_reg;
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}
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s->sys_cfgctrl = val & ~(3 << 18);
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s->sys_cfgstat = 1; /* complete */
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switch (s->sys_cfgctrl) {
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case 0xc0800000: /* SYS_CFG_SHUTDOWN to motherboard */
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qemu_system_shutdown_request();
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break;
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case 0xc0900000: /* SYS_CFG_REBOOT to motherboard */
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qemu_system_reset_request();
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break;
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default:
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s->sys_cfgstat |= 2; /* error */
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/* Undefined bits [19:18] are RAZ/WI, and writing to
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* the start bit just triggers the action; it always reads
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* as zero.
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*/
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s->sys_cfgctrl = val & ~((3 << 18) | (1 << 31));
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if (val & (1 << 31)) {
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/* Start bit set -- actually do something */
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unsigned int dcc = extract32(s->sys_cfgctrl, 26, 4);
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unsigned int function = extract32(s->sys_cfgctrl, 20, 6);
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unsigned int site = extract32(s->sys_cfgctrl, 16, 2);
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unsigned int position = extract32(s->sys_cfgctrl, 12, 4);
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unsigned int device = extract32(s->sys_cfgctrl, 0, 12);
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s->sys_cfgstat = 1; /* complete */
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if (s->sys_cfgctrl & (1 << 30)) {
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if (!vexpress_cfgctrl_write(s, dcc, function, site, position,
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device, s->sys_cfgdata)) {
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s->sys_cfgstat |= 2; /* error */
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}
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} else {
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uint32_t val;
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if (!vexpress_cfgctrl_read(s, dcc, function, site, position,
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device, &val)) {
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s->sys_cfgstat |= 2; /* error */
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} else {
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s->sys_cfgdata = val;
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}
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}
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}
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s->sys_cfgctrl &= ~(1 << 31);
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return;
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