mirror of https://github.com/xemu-project/xemu.git
target/mips: Style improvements in translate.c
Fixes mostly errors and warnings reported by 'checkpatch.pl -f'. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1566216496-17375-12-git-send-email-aleksandar.markovic@rt-rk.com>
This commit is contained in:
Aleksandar Markovic
parent
eca3cbb847
commit
71375b5924
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@ -170,7 +170,7 @@ enum {
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};
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/* MIPS special opcodes */
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#define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F)
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#define MASK_SPECIAL(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
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enum {
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/* Shifts */
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@ -295,7 +295,7 @@ enum {
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};
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/* Multiplication variants of the vr54xx. */
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#define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6))
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#define MASK_MUL_VR54XX(op) (MASK_SPECIAL(op) | (op & (0x1F << 6)))
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enum {
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OPC_VR54XX_MULS = (0x03 << 6) | OPC_MULT,
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@ -315,7 +315,7 @@ enum {
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};
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/* REGIMM (rt field) opcodes */
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#define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
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#define MASK_REGIMM(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 16)))
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enum {
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OPC_BLTZ = (0x00 << 16) | OPC_REGIMM,
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@ -340,7 +340,7 @@ enum {
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};
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/* Special2 opcodes */
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#define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F)
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#define MASK_SPECIAL2(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
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enum {
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/* Multiply & xxx operations */
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@ -372,7 +372,7 @@ enum {
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};
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/* Special3 opcodes */
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#define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
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#define MASK_SPECIAL3(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
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enum {
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OPC_EXT = 0x00 | OPC_SPECIAL3,
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@ -460,7 +460,7 @@ enum {
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};
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/* BSHFL opcodes */
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#define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
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#define MASK_BSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
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enum {
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OPC_WSBH = (0x02 << 6) | OPC_BSHFL,
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@ -474,7 +474,7 @@ enum {
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};
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/* DBSHFL opcodes */
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#define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
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#define MASK_DBSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
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enum {
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OPC_DSBH = (0x02 << 6) | OPC_DBSHFL,
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@ -898,7 +898,7 @@ enum {
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};
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/* Coprocessor 0 (rs field) */
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#define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
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#define MASK_CP0(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
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enum {
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OPC_MFC0 = (0x00 << 21) | OPC_CP0,
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@ -931,7 +931,7 @@ enum {
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};
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/* MFMC0 opcodes */
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#define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
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#define MASK_MFMC0(op) (MASK_CP0(op) | (op & 0xFFFF))
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enum {
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OPC_DMT = 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,
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@ -945,7 +945,7 @@ enum {
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};
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/* Coprocessor 0 (with rs == C0) */
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#define MASK_C0(op) MASK_CP0(op) | (op & 0x3F)
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#define MASK_C0(op) (MASK_CP0(op) | (op & 0x3F))
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enum {
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OPC_TLBR = 0x01 | OPC_C0,
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@ -961,7 +961,7 @@ enum {
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};
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/* Coprocessor 1 (rs field) */
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#define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
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#define MASK_CP1(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
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/* Values for the fmt field in FP instructions */
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enum {
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@ -1009,8 +1009,8 @@ enum {
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OPC_BNZ_D = (0x1F << 21) | OPC_CP1,
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};
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#define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
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#define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16))
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#define MASK_CP1_FUNC(op) (MASK_CP1(op) | (op & 0x3F))
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#define MASK_BC1(op) (MASK_CP1(op) | (op & (0x3 << 16)))
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enum {
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OPC_BC1F = (0x00 << 16) | OPC_BC1,
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@ -1029,7 +1029,7 @@ enum {
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OPC_BC1TANY4 = (0x01 << 16) | OPC_BC1ANY4,
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};
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#define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
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#define MASK_CP2(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
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enum {
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OPC_MFC2 = (0x00 << 21) | OPC_CP2,
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@ -1142,7 +1142,7 @@ enum {
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};
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#define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
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#define MASK_CP3(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
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enum {
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OPC_LWXC1 = 0x00 | OPC_CP3,
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@ -1161,10 +1161,10 @@ enum {
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OPC_MSUB_PS = 0x2E | OPC_CP3,
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OPC_NMADD_S = 0x30 | OPC_CP3,
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OPC_NMADD_D = 0x31 | OPC_CP3,
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OPC_NMADD_PS= 0x36 | OPC_CP3,
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OPC_NMADD_PS = 0x36 | OPC_CP3,
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OPC_NMSUB_S = 0x38 | OPC_CP3,
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OPC_NMSUB_D = 0x39 | OPC_CP3,
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OPC_NMSUB_PS= 0x3E | OPC_CP3,
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OPC_NMSUB_PS = 0x3E | OPC_CP3,
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};
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/* MSA Opcodes */
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@ -2476,43 +2476,43 @@ static TCGv mxu_CR;
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TCGv_i32 helper_tmp = tcg_const_i32(arg); \
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gen_helper_##name(cpu_env, helper_tmp); \
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tcg_temp_free_i32(helper_tmp); \
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} while(0)
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} while (0)
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#define gen_helper_0e1i(name, arg1, arg2) do { \
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TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
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gen_helper_##name(cpu_env, arg1, helper_tmp); \
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tcg_temp_free_i32(helper_tmp); \
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} while(0)
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} while (0)
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#define gen_helper_1e0i(name, ret, arg1) do { \
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TCGv_i32 helper_tmp = tcg_const_i32(arg1); \
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gen_helper_##name(ret, cpu_env, helper_tmp); \
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tcg_temp_free_i32(helper_tmp); \
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} while(0)
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} while (0)
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#define gen_helper_1e1i(name, ret, arg1, arg2) do { \
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TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
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gen_helper_##name(ret, cpu_env, arg1, helper_tmp); \
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tcg_temp_free_i32(helper_tmp); \
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} while(0)
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} while (0)
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#define gen_helper_0e2i(name, arg1, arg2, arg3) do { \
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TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
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gen_helper_##name(cpu_env, arg1, arg2, helper_tmp); \
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tcg_temp_free_i32(helper_tmp); \
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} while(0)
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} while (0)
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#define gen_helper_1e2i(name, ret, arg1, arg2, arg3) do { \
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TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
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gen_helper_##name(ret, cpu_env, arg1, arg2, helper_tmp); \
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tcg_temp_free_i32(helper_tmp); \
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} while(0)
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} while (0)
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#define gen_helper_0e3i(name, arg1, arg2, arg3, arg4) do { \
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TCGv_i32 helper_tmp = tcg_const_i32(arg4); \
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gen_helper_##name(cpu_env, arg1, arg2, arg3, helper_tmp); \
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tcg_temp_free_i32(helper_tmp); \
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} while(0)
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} while (0)
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typedef struct DisasContext {
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DisasContextBase base;
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@ -2661,7 +2661,7 @@ static inline void gen_load_srsgpr(int from, int to)
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tcg_temp_free(t0);
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}
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static inline void gen_store_srsgpr (int from, int to)
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static inline void gen_store_srsgpr(int from, int to)
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{
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if (to != 0) {
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TCGv t0 = tcg_temp_new();
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@ -3181,8 +3181,8 @@ static inline void check_eva(DisasContext *ctx)
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static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \
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int ft, int fs, int cc) \
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{ \
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TCGv_i##bits fp0 = tcg_temp_new_i##bits (); \
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TCGv_i##bits fp1 = tcg_temp_new_i##bits (); \
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TCGv_i##bits fp0 = tcg_temp_new_i##bits(); \
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TCGv_i##bits fp1 = tcg_temp_new_i##bits(); \
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switch (ifmt) { \
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case FMT_PS: \
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check_ps(ctx); \
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@ -3199,8 +3199,8 @@ static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \
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} \
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break; \
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} \
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gen_ldcmp_fpr##bits (ctx, fp0, fs); \
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gen_ldcmp_fpr##bits (ctx, fp1, ft); \
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gen_ldcmp_fpr##bits(ctx, fp0, fs); \
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gen_ldcmp_fpr##bits(ctx, fp1, ft); \
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switch (n) { \
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case 0: \
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gen_helper_0e2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); \
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@ -3253,8 +3253,8 @@ static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \
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default: \
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abort(); \
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} \
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tcg_temp_free_i##bits (fp0); \
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tcg_temp_free_i##bits (fp1); \
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tcg_temp_free_i##bits(fp0); \
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tcg_temp_free_i##bits(fp1); \
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}
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FOP_CONDS(, 0, d, FMT_D, 64)
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@ -3266,7 +3266,7 @@ FOP_CONDS(abs, 1, ps, FMT_PS, 64)
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#undef FOP_CONDS
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#define FOP_CONDNS(fmt, ifmt, bits, STORE) \
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static inline void gen_r6_cmp_ ## fmt(DisasContext * ctx, int n, \
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static inline void gen_r6_cmp_ ## fmt(DisasContext *ctx, int n, \
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int ft, int fs, int fd) \
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{ \
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TCGv_i ## bits fp0 = tcg_temp_new_i ## bits(); \
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@ -3347,8 +3347,8 @@ static inline void gen_r6_cmp_ ## fmt(DisasContext * ctx, int n, \
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abort(); \
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} \
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STORE; \
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tcg_temp_free_i ## bits (fp0); \
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tcg_temp_free_i ## bits (fp1); \
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tcg_temp_free_i ## bits(fp0); \
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tcg_temp_free_i ## bits(fp1); \
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}
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FOP_CONDNS(d, FMT_D, 64, gen_store_fpr64(ctx, fp0, fd))
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@ -3359,7 +3359,7 @@ FOP_CONDNS(s, FMT_S, 32, gen_store_fpr32(ctx, fp0, fd))
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/* load/store instructions. */
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#ifdef CONFIG_USER_ONLY
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#define OP_LD_ATOMIC(insn,fname) \
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#define OP_LD_ATOMIC(insn, fname) \
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static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
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DisasContext *ctx) \
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{ \
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@ -3371,16 +3371,16 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
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tcg_temp_free(t0); \
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}
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#else
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#define OP_LD_ATOMIC(insn,fname) \
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#define OP_LD_ATOMIC(insn, fname) \
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static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
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DisasContext *ctx) \
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{ \
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gen_helper_1e1i(insn, ret, arg1, mem_idx); \
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}
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#endif
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OP_LD_ATOMIC(ll,ld32s);
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OP_LD_ATOMIC(ll, ld32s);
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#if defined(TARGET_MIPS64)
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OP_LD_ATOMIC(lld,ld64);
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OP_LD_ATOMIC(lld, ld64);
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#endif
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#undef OP_LD_ATOMIC
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@ -4227,7 +4227,10 @@ static void gen_arith(DisasContext *ctx, uint32_t opc,
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tcg_temp_free(t2);
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tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
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tcg_temp_free(t1);
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/* operands of different sign, first operand and result different sign */
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/*
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* Operands of different sign, first operand and result different
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* sign.
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*/
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generate_exception(ctx, EXCP_OVERFLOW);
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gen_set_label(l1);
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gen_store_gpr(t0, rd);
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@ -5777,7 +5780,7 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
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}
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/* Traps */
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static void gen_trap (DisasContext *ctx, uint32_t opc,
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static void gen_trap(DisasContext *ctx, uint32_t opc,
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int rs, int rt, int16_t imm)
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{
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int cond;
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@ -5900,7 +5903,7 @@ static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
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}
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/* Branches (before delay slot) */
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static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
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static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
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int insn_bytes,
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int rs, int rt, int32_t offset,
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int delayslot_size)
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@ -9731,7 +9734,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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case 7:
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CP0_CHECK(ctx->kscrexist & (1 << sel));
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tcg_gen_st_tl(arg, cpu_env,
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offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
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offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
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register_name = "KScratch";
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break;
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default:
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@ -9897,7 +9900,8 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
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default:
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gen_mfc0(ctx, t0, rt, sel);
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}
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} else switch (sel) {
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} else {
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switch (sel) {
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/* GPR registers. */
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case 0:
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gen_helper_1e0i(mftgpr, t0, rt);
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@ -9976,6 +9980,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
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default:
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goto die;
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}
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}
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trace_mips_translate_tr("mftr", rt, u, sel, h);
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gen_store_gpr(t0, rd);
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tcg_temp_free(t0);
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@ -10099,7 +10104,8 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
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default:
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gen_mtc0(ctx, t0, rd, sel);
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}
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} else switch (sel) {
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} else {
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switch (sel) {
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/* GPR registers. */
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case 0:
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gen_helper_0e1i(mttgpr, t0, rd);
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@ -10185,6 +10191,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
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default:
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goto die;
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}
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}
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trace_mips_translate_tr("mttr", rd, u, sel, h);
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tcg_temp_free(t0);
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return;
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@ -10429,7 +10436,7 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
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{
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TCGv_i32 t1 = tcg_temp_new_i32();
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tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
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tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1));
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tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1));
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tcg_gen_nand_i32(t0, t0, t1);
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tcg_temp_free_i32(t1);
|
||||
tcg_gen_andi_i32(t0, t0, 1);
|
||||
|
|
@ -10440,7 +10447,7 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
|
|||
{
|
||||
TCGv_i32 t1 = tcg_temp_new_i32();
|
||||
tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
|
||||
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1));
|
||||
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1));
|
||||
tcg_gen_or_i32(t0, t0, t1);
|
||||
tcg_temp_free_i32(t1);
|
||||
tcg_gen_andi_i32(t0, t0, 1);
|
||||
|
|
@ -10451,11 +10458,11 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
|
|||
{
|
||||
TCGv_i32 t1 = tcg_temp_new_i32();
|
||||
tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
|
||||
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1));
|
||||
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1));
|
||||
tcg_gen_and_i32(t0, t0, t1);
|
||||
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2));
|
||||
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 2));
|
||||
tcg_gen_and_i32(t0, t0, t1);
|
||||
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3));
|
||||
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 3));
|
||||
tcg_gen_nand_i32(t0, t0, t1);
|
||||
tcg_temp_free_i32(t1);
|
||||
tcg_gen_andi_i32(t0, t0, 1);
|
||||
|
|
@ -10466,11 +10473,11 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
|
|||
{
|
||||
TCGv_i32 t1 = tcg_temp_new_i32();
|
||||
tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
|
||||
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1));
|
||||
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1));
|
||||
tcg_gen_or_i32(t0, t0, t1);
|
||||
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2));
|
||||
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 2));
|
||||
tcg_gen_or_i32(t0, t0, t1);
|
||||
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3));
|
||||
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 3));
|
||||
tcg_gen_or_i32(t0, t0, t1);
|
||||
tcg_temp_free_i32(t1);
|
||||
tcg_gen_andi_i32(t0, t0, 1);
|
||||
|
|
@ -10934,7 +10941,7 @@ static inline void gen_movcf_ps(DisasContext *ctx, int fs, int fd,
|
|||
gen_store_fpr32(ctx, t0, fd);
|
||||
gen_set_label(l1);
|
||||
|
||||
tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc+1));
|
||||
tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc + 1));
|
||||
tcg_gen_brcondi_i32(cond, t0, 0, l2);
|
||||
gen_load_fpr32h(ctx, t0, fs);
|
||||
gen_store_fpr32h(ctx, t0, fd);
|
||||
|
|
@ -11548,9 +11555,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
|
|||
case OPC_CMP_NGT_S:
|
||||
check_insn_opc_removed(ctx, ISA_MIPS32R6);
|
||||
if (ctx->opcode & (1 << 6)) {
|
||||
gen_cmpabs_s(ctx, func-48, ft, fs, cc);
|
||||
gen_cmpabs_s(ctx, func - 48, ft, fs, cc);
|
||||
} else {
|
||||
gen_cmp_s(ctx, func-48, ft, fs, cc);
|
||||
gen_cmp_s(ctx, func - 48, ft, fs, cc);
|
||||
}
|
||||
break;
|
||||
case OPC_ADD_D:
|
||||
|
|
@ -12030,9 +12037,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
|
|||
case OPC_CMP_NGT_D:
|
||||
check_insn_opc_removed(ctx, ISA_MIPS32R6);
|
||||
if (ctx->opcode & (1 << 6)) {
|
||||
gen_cmpabs_d(ctx, func-48, ft, fs, cc);
|
||||
gen_cmpabs_d(ctx, func - 48, ft, fs, cc);
|
||||
} else {
|
||||
gen_cmp_d(ctx, func-48, ft, fs, cc);
|
||||
gen_cmp_d(ctx, func - 48, ft, fs, cc);
|
||||
}
|
||||
break;
|
||||
case OPC_CVT_S_D:
|
||||
|
|
@ -12432,9 +12439,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
|
|||
case OPC_CMP_LE_PS:
|
||||
case OPC_CMP_NGT_PS:
|
||||
if (ctx->opcode & (1 << 6)) {
|
||||
gen_cmpabs_ps(ctx, func-48, ft, fs, cc);
|
||||
gen_cmpabs_ps(ctx, func - 48, ft, fs, cc);
|
||||
} else {
|
||||
gen_cmp_ps(ctx, func-48, ft, fs, cc);
|
||||
gen_cmp_ps(ctx, func - 48, ft, fs, cc);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
|
|
@ -14247,7 +14254,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
|
|||
case RR_RY_CNVT_SEH:
|
||||
tcg_gen_ext16s_tl(cpu_gpr[rx], cpu_gpr[rx]);
|
||||
break;
|
||||
#if defined (TARGET_MIPS64)
|
||||
#if defined(TARGET_MIPS64)
|
||||
case RR_RY_CNVT_ZEW:
|
||||
check_insn(ctx, ISA_MIPS64);
|
||||
check_mips_64(ctx);
|
||||
|
|
@ -14971,11 +14978,11 @@ static int mmreg2(int r)
|
|||
|
||||
/* Signed immediate */
|
||||
#define SIMM(op, start, width) \
|
||||
((int32_t)(((op >> start) & ((~0U) >> (32-width))) \
|
||||
<< (32-width)) \
|
||||
>> (32-width))
|
||||
((int32_t)(((op >> start) & ((~0U) >> (32 - width))) \
|
||||
<< (32 - width)) \
|
||||
>> (32 - width))
|
||||
/* Zero-extended immediate */
|
||||
#define ZIMM(op, start, width) ((op >> start) & ((~0U) >> (32-width)))
|
||||
#define ZIMM(op, start, width) ((op >> start) & ((~0U) >> (32 - width)))
|
||||
|
||||
static void gen_addiur1sp(DisasContext *ctx)
|
||||
{
|
||||
|
|
@ -15669,7 +15676,10 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
|
|||
save_cpu_state(ctx, 1);
|
||||
gen_helper_di(t0, cpu_env);
|
||||
gen_store_gpr(t0, rs);
|
||||
/* Stop translation as we may have switched the execution mode */
|
||||
/*
|
||||
* Stop translation as we may have switched the execution
|
||||
* mode.
|
||||
*/
|
||||
ctx->base.is_jmp = DISAS_STOP;
|
||||
tcg_temp_free(t0);
|
||||
}
|
||||
|
|
@ -15791,9 +15801,9 @@ static void gen_pool32fxf(DisasContext *ctx, int rt, int rs)
|
|||
int extension = (ctx->opcode >> 6) & 0x3ff;
|
||||
uint32_t mips32_op;
|
||||
|
||||
#define FLOAT_1BIT_FMT(opc, fmt) (fmt << 8) | opc
|
||||
#define FLOAT_2BIT_FMT(opc, fmt) (fmt << 7) | opc
|
||||
#define COND_FLOAT_MOV(opc, cond) (cond << 7) | opc
|
||||
#define FLOAT_1BIT_FMT(opc, fmt) ((fmt << 8) | opc)
|
||||
#define FLOAT_2BIT_FMT(opc, fmt) ((fmt << 7) | opc)
|
||||
#define COND_FLOAT_MOV(opc, cond) ((cond << 7) | opc)
|
||||
|
||||
switch (extension) {
|
||||
case FLOAT_1BIT_FMT(CFC1, 0):
|
||||
|
|
@ -30128,7 +30138,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
|
|||
translator_loop(&mips_tr_ops, &ctx.base, cs, tb, max_insns);
|
||||
}
|
||||
|
||||
static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags)
|
||||
static void fpu_dump_state(CPUMIPSState *env, FILE * f, int flags)
|
||||
{
|
||||
int i;
|
||||
int is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64);
|
||||
|
|
@ -30153,7 +30163,7 @@ static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags)
|
|||
(double)tmp.fs[FP_ENDIAN_IDX], \
|
||||
(double)tmp.fs[!FP_ENDIAN_IDX]); \
|
||||
} \
|
||||
} while(0)
|
||||
} while (0)
|
||||
|
||||
|
||||
qemu_fprintf(f,
|
||||
|
|
@ -30190,7 +30200,8 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
|
|||
}
|
||||
}
|
||||
|
||||
qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx "\n",
|
||||
qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x"
|
||||
TARGET_FMT_lx "\n",
|
||||
env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
|
||||
qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016"
|
||||
PRIx64 "\n",
|
||||
|
|
@ -30211,7 +30222,8 @@ void mips_tcg_init(void)
|
|||
cpu_gpr[0] = NULL;
|
||||
for (i = 1; i < 32; i++)
|
||||
cpu_gpr[i] = tcg_global_mem_new(cpu_env,
|
||||
offsetof(CPUMIPSState, active_tc.gpr[i]),
|
||||
offsetof(CPUMIPSState,
|
||||
active_tc.gpr[i]),
|
||||
regnames[i]);
|
||||
|
||||
for (i = 0; i < 32; i++) {
|
||||
|
|
@ -30239,7 +30251,8 @@ void mips_tcg_init(void)
|
|||
regnames_LO[i]);
|
||||
}
|
||||
cpu_dspctrl = tcg_global_mem_new(cpu_env,
|
||||
offsetof(CPUMIPSState, active_tc.DSPControl),
|
||||
offsetof(CPUMIPSState,
|
||||
active_tc.DSPControl),
|
||||
"DSPControl");
|
||||
bcond = tcg_global_mem_new(cpu_env,
|
||||
offsetof(CPUMIPSState, bcond), "bcond");
|
||||
|
|
|
|||
Loading…
Reference in New Issue