mirror of https://github.com/xemu-project/xemu.git
target/mips: Style improvements in translate.c
Fixes mostly errors and warnings reported by 'checkpatch.pl -f'. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1566216496-17375-12-git-send-email-aleksandar.markovic@rt-rk.com>
This commit is contained in:
Aleksandar Markovic
parent
eca3cbb847
commit
71375b5924
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@ -170,7 +170,7 @@ enum {
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};
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/* MIPS special opcodes */
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#define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F)
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#define MASK_SPECIAL(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
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enum {
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/* Shifts */
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@ -295,7 +295,7 @@ enum {
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};
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/* Multiplication variants of the vr54xx. */
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#define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6))
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#define MASK_MUL_VR54XX(op) (MASK_SPECIAL(op) | (op & (0x1F << 6)))
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enum {
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OPC_VR54XX_MULS = (0x03 << 6) | OPC_MULT,
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@ -315,7 +315,7 @@ enum {
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};
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/* REGIMM (rt field) opcodes */
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#define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
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#define MASK_REGIMM(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 16)))
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enum {
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OPC_BLTZ = (0x00 << 16) | OPC_REGIMM,
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@ -340,7 +340,7 @@ enum {
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};
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/* Special2 opcodes */
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#define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F)
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#define MASK_SPECIAL2(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
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enum {
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/* Multiply & xxx operations */
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@ -372,7 +372,7 @@ enum {
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};
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/* Special3 opcodes */
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#define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
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#define MASK_SPECIAL3(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
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enum {
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OPC_EXT = 0x00 | OPC_SPECIAL3,
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@ -460,7 +460,7 @@ enum {
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};
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/* BSHFL opcodes */
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#define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
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#define MASK_BSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
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enum {
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OPC_WSBH = (0x02 << 6) | OPC_BSHFL,
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@ -474,7 +474,7 @@ enum {
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};
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/* DBSHFL opcodes */
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#define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
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#define MASK_DBSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
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enum {
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OPC_DSBH = (0x02 << 6) | OPC_DBSHFL,
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@ -898,7 +898,7 @@ enum {
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};
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/* Coprocessor 0 (rs field) */
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#define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
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#define MASK_CP0(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
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enum {
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OPC_MFC0 = (0x00 << 21) | OPC_CP0,
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@ -931,7 +931,7 @@ enum {
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};
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/* MFMC0 opcodes */
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#define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
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#define MASK_MFMC0(op) (MASK_CP0(op) | (op & 0xFFFF))
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enum {
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OPC_DMT = 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,
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@ -945,7 +945,7 @@ enum {
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};
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/* Coprocessor 0 (with rs == C0) */
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#define MASK_C0(op) MASK_CP0(op) | (op & 0x3F)
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#define MASK_C0(op) (MASK_CP0(op) | (op & 0x3F))
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enum {
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OPC_TLBR = 0x01 | OPC_C0,
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@ -961,7 +961,7 @@ enum {
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};
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/* Coprocessor 1 (rs field) */
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#define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
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#define MASK_CP1(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
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/* Values for the fmt field in FP instructions */
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enum {
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@ -1009,8 +1009,8 @@ enum {
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OPC_BNZ_D = (0x1F << 21) | OPC_CP1,
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};
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#define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
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#define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16))
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#define MASK_CP1_FUNC(op) (MASK_CP1(op) | (op & 0x3F))
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#define MASK_BC1(op) (MASK_CP1(op) | (op & (0x3 << 16)))
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enum {
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OPC_BC1F = (0x00 << 16) | OPC_BC1,
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@ -1029,7 +1029,7 @@ enum {
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OPC_BC1TANY4 = (0x01 << 16) | OPC_BC1ANY4,
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};
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#define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
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#define MASK_CP2(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
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enum {
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OPC_MFC2 = (0x00 << 21) | OPC_CP2,
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@ -1142,7 +1142,7 @@ enum {
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};
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#define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
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#define MASK_CP3(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
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enum {
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OPC_LWXC1 = 0x00 | OPC_CP3,
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@ -4227,7 +4227,10 @@ static void gen_arith(DisasContext *ctx, uint32_t opc,
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tcg_temp_free(t2);
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tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
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tcg_temp_free(t1);
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/* operands of different sign, first operand and result different sign */
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/*
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* Operands of different sign, first operand and result different
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* sign.
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*/
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generate_exception(ctx, EXCP_OVERFLOW);
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gen_set_label(l1);
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gen_store_gpr(t0, rd);
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@ -9897,7 +9900,8 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
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default:
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gen_mfc0(ctx, t0, rt, sel);
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}
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} else switch (sel) {
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} else {
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switch (sel) {
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/* GPR registers. */
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case 0:
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gen_helper_1e0i(mftgpr, t0, rt);
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@ -9976,6 +9980,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
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default:
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goto die;
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}
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}
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trace_mips_translate_tr("mftr", rt, u, sel, h);
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gen_store_gpr(t0, rd);
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tcg_temp_free(t0);
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@ -10099,7 +10104,8 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
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default:
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gen_mtc0(ctx, t0, rd, sel);
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}
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} else switch (sel) {
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} else {
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switch (sel) {
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/* GPR registers. */
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case 0:
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gen_helper_0e1i(mttgpr, t0, rd);
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@ -10185,6 +10191,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
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default:
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goto die;
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}
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}
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trace_mips_translate_tr("mttr", rd, u, sel, h);
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tcg_temp_free(t0);
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return;
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@ -15669,7 +15676,10 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
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save_cpu_state(ctx, 1);
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gen_helper_di(t0, cpu_env);
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gen_store_gpr(t0, rs);
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/* Stop translation as we may have switched the execution mode */
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/*
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* Stop translation as we may have switched the execution
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* mode.
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*/
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ctx->base.is_jmp = DISAS_STOP;
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tcg_temp_free(t0);
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}
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@ -15791,9 +15801,9 @@ static void gen_pool32fxf(DisasContext *ctx, int rt, int rs)
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int extension = (ctx->opcode >> 6) & 0x3ff;
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uint32_t mips32_op;
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#define FLOAT_1BIT_FMT(opc, fmt) (fmt << 8) | opc
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#define FLOAT_2BIT_FMT(opc, fmt) (fmt << 7) | opc
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#define COND_FLOAT_MOV(opc, cond) (cond << 7) | opc
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#define FLOAT_1BIT_FMT(opc, fmt) ((fmt << 8) | opc)
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#define FLOAT_2BIT_FMT(opc, fmt) ((fmt << 7) | opc)
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#define COND_FLOAT_MOV(opc, cond) ((cond << 7) | opc)
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switch (extension) {
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case FLOAT_1BIT_FMT(CFC1, 0):
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@ -30190,7 +30200,8 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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}
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}
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qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx "\n",
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qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x"
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TARGET_FMT_lx "\n",
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env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
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qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016"
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PRIx64 "\n",
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@ -30211,7 +30222,8 @@ void mips_tcg_init(void)
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cpu_gpr[0] = NULL;
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for (i = 1; i < 32; i++)
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cpu_gpr[i] = tcg_global_mem_new(cpu_env,
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offsetof(CPUMIPSState, active_tc.gpr[i]),
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offsetof(CPUMIPSState,
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active_tc.gpr[i]),
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regnames[i]);
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for (i = 0; i < 32; i++) {
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@ -30239,7 +30251,8 @@ void mips_tcg_init(void)
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regnames_LO[i]);
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}
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cpu_dspctrl = tcg_global_mem_new(cpu_env,
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offsetof(CPUMIPSState, active_tc.DSPControl),
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offsetof(CPUMIPSState,
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active_tc.DSPControl),
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"DSPControl");
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bcond = tcg_global_mem_new(cpu_env,
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offsetof(CPUMIPSState, bcond), "bcond");
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