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target/mips: Style improvements in translate.c 

Fixes mostly errors and warnings reported by 'checkpatch.pl -f'.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1566216496-17375-12-git-send-email-aleksandar.markovic@rt-rk.com>
This commit is contained in:
Aleksandar Markovic 2019-08-19 14:07:50 +02:00
parent eca3cbb847
commit 71375b5924
1 changed files with 382 additions and 369 deletions
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159
target/mips/translate.c
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@ -170,7 +170,7 @@ enum {
}; };
/* MIPS special opcodes */ /* MIPS special opcodes */
#define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F) #define MASK_SPECIAL(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
enum { enum {
/* Shifts */ /* Shifts */
@ -295,7 +295,7 @@ enum {
}; };
/* Multiplication variants of the vr54xx. */ /* Multiplication variants of the vr54xx. */
#define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6)) #define MASK_MUL_VR54XX(op) (MASK_SPECIAL(op) | (op & (0x1F << 6)))
enum { enum {
OPC_VR54XX_MULS = (0x03 << 6) | OPC_MULT, OPC_VR54XX_MULS = (0x03 << 6) | OPC_MULT,
@ -315,7 +315,7 @@ enum {
}; };
/* REGIMM (rt field) opcodes */ /* REGIMM (rt field) opcodes */
#define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16)) #define MASK_REGIMM(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 16)))
enum { enum {
OPC_BLTZ = (0x00 << 16) | OPC_REGIMM, OPC_BLTZ = (0x00 << 16) | OPC_REGIMM,
@ -340,7 +340,7 @@ enum {
}; };
/* Special2 opcodes */ /* Special2 opcodes */
#define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F) #define MASK_SPECIAL2(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
enum { enum {
/* Multiply & xxx operations */ /* Multiply & xxx operations */
@ -372,7 +372,7 @@ enum {
}; };
/* Special3 opcodes */ /* Special3 opcodes */
#define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F) #define MASK_SPECIAL3(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
enum { enum {
OPC_EXT = 0x00 | OPC_SPECIAL3, OPC_EXT = 0x00 | OPC_SPECIAL3,
@ -460,7 +460,7 @@ enum {
}; };
/* BSHFL opcodes */ /* BSHFL opcodes */
#define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6)) #define MASK_BSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
enum { enum {
OPC_WSBH = (0x02 << 6) | OPC_BSHFL, OPC_WSBH = (0x02 << 6) | OPC_BSHFL,
@ -474,7 +474,7 @@ enum {
}; };
/* DBSHFL opcodes */ /* DBSHFL opcodes */
#define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6)) #define MASK_DBSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
enum { enum {
OPC_DSBH = (0x02 << 6) | OPC_DBSHFL, OPC_DSBH = (0x02 << 6) | OPC_DBSHFL,
@ -898,7 +898,7 @@ enum {
}; };
/* Coprocessor 0 (rs field) */ /* Coprocessor 0 (rs field) */
#define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) #define MASK_CP0(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
enum { enum {
OPC_MFC0 = (0x00 << 21) | OPC_CP0, OPC_MFC0 = (0x00 << 21) | OPC_CP0,
@ -931,7 +931,7 @@ enum {
}; };
/* MFMC0 opcodes */ /* MFMC0 opcodes */
#define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF) #define MASK_MFMC0(op) (MASK_CP0(op) | (op & 0xFFFF))
enum { enum {
OPC_DMT = 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0, OPC_DMT = 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,
@ -945,7 +945,7 @@ enum {
}; };
/* Coprocessor 0 (with rs == C0) */ /* Coprocessor 0 (with rs == C0) */
#define MASK_C0(op) MASK_CP0(op) | (op & 0x3F) #define MASK_C0(op) (MASK_CP0(op) | (op & 0x3F))
enum { enum {
OPC_TLBR = 0x01 | OPC_C0, OPC_TLBR = 0x01 | OPC_C0,
@ -961,7 +961,7 @@ enum {
}; };
/* Coprocessor 1 (rs field) */ /* Coprocessor 1 (rs field) */
#define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) #define MASK_CP1(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
/* Values for the fmt field in FP instructions */ /* Values for the fmt field in FP instructions */
enum { enum {
@ -1009,8 +1009,8 @@ enum {
OPC_BNZ_D = (0x1F << 21) | OPC_CP1, OPC_BNZ_D = (0x1F << 21) | OPC_CP1,
}; };
#define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F) #define MASK_CP1_FUNC(op) (MASK_CP1(op) | (op & 0x3F))
#define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16)) #define MASK_BC1(op) (MASK_CP1(op) | (op & (0x3 << 16)))
enum { enum {
OPC_BC1F = (0x00 << 16) | OPC_BC1, OPC_BC1F = (0x00 << 16) | OPC_BC1,
@ -1029,7 +1029,7 @@ enum {
OPC_BC1TANY4 = (0x01 << 16) | OPC_BC1ANY4, OPC_BC1TANY4 = (0x01 << 16) | OPC_BC1ANY4,
}; };
#define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) #define MASK_CP2(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
enum { enum {
OPC_MFC2 = (0x00 << 21) | OPC_CP2, OPC_MFC2 = (0x00 << 21) | OPC_CP2,
@ -1142,7 +1142,7 @@ enum {
}; };
#define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F) #define MASK_CP3(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
enum { enum {
OPC_LWXC1 = 0x00 | OPC_CP3, OPC_LWXC1 = 0x00 | OPC_CP3,
@ -1161,10 +1161,10 @@ enum {
OPC_MSUB_PS = 0x2E | OPC_CP3, OPC_MSUB_PS = 0x2E | OPC_CP3,
OPC_NMADD_S = 0x30 | OPC_CP3, OPC_NMADD_S = 0x30 | OPC_CP3,
OPC_NMADD_D = 0x31 | OPC_CP3, OPC_NMADD_D = 0x31 | OPC_CP3,
OPC_NMADD_PS= 0x36 | OPC_CP3, OPC_NMADD_PS = 0x36 | OPC_CP3,
OPC_NMSUB_S = 0x38 | OPC_CP3, OPC_NMSUB_S = 0x38 | OPC_CP3,
OPC_NMSUB_D = 0x39 | OPC_CP3, OPC_NMSUB_D = 0x39 | OPC_CP3,
OPC_NMSUB_PS= 0x3E | OPC_CP3, OPC_NMSUB_PS = 0x3E | OPC_CP3,
}; };
/* MSA Opcodes */ /* MSA Opcodes */
@ -2476,43 +2476,43 @@ static TCGv mxu_CR;
TCGv_i32 helper_tmp = tcg_const_i32(arg); \ TCGv_i32 helper_tmp = tcg_const_i32(arg); \
gen_helper_##name(cpu_env, helper_tmp); \ gen_helper_##name(cpu_env, helper_tmp); \
tcg_temp_free_i32(helper_tmp); \ tcg_temp_free_i32(helper_tmp); \
} while(0) } while (0)
#define gen_helper_0e1i(name, arg1, arg2) do { \ #define gen_helper_0e1i(name, arg1, arg2) do { \
TCGv_i32 helper_tmp = tcg_const_i32(arg2); \ TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
gen_helper_##name(cpu_env, arg1, helper_tmp); \ gen_helper_##name(cpu_env, arg1, helper_tmp); \
tcg_temp_free_i32(helper_tmp); \ tcg_temp_free_i32(helper_tmp); \
} while(0) } while (0)
#define gen_helper_1e0i(name, ret, arg1) do { \ #define gen_helper_1e0i(name, ret, arg1) do { \
TCGv_i32 helper_tmp = tcg_const_i32(arg1); \ TCGv_i32 helper_tmp = tcg_const_i32(arg1); \
gen_helper_##name(ret, cpu_env, helper_tmp); \ gen_helper_##name(ret, cpu_env, helper_tmp); \
tcg_temp_free_i32(helper_tmp); \ tcg_temp_free_i32(helper_tmp); \
} while(0) } while (0)
#define gen_helper_1e1i(name, ret, arg1, arg2) do { \ #define gen_helper_1e1i(name, ret, arg1, arg2) do { \
TCGv_i32 helper_tmp = tcg_const_i32(arg2); \ TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
gen_helper_##name(ret, cpu_env, arg1, helper_tmp); \ gen_helper_##name(ret, cpu_env, arg1, helper_tmp); \
tcg_temp_free_i32(helper_tmp); \ tcg_temp_free_i32(helper_tmp); \
} while(0) } while (0)
#define gen_helper_0e2i(name, arg1, arg2, arg3) do { \ #define gen_helper_0e2i(name, arg1, arg2, arg3) do { \
TCGv_i32 helper_tmp = tcg_const_i32(arg3); \ TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
gen_helper_##name(cpu_env, arg1, arg2, helper_tmp); \ gen_helper_##name(cpu_env, arg1, arg2, helper_tmp); \
tcg_temp_free_i32(helper_tmp); \ tcg_temp_free_i32(helper_tmp); \
} while(0) } while (0)
#define gen_helper_1e2i(name, ret, arg1, arg2, arg3) do { \ #define gen_helper_1e2i(name, ret, arg1, arg2, arg3) do { \
TCGv_i32 helper_tmp = tcg_const_i32(arg3); \ TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
gen_helper_##name(ret, cpu_env, arg1, arg2, helper_tmp); \ gen_helper_##name(ret, cpu_env, arg1, arg2, helper_tmp); \
tcg_temp_free_i32(helper_tmp); \ tcg_temp_free_i32(helper_tmp); \
} while(0) } while (0)
#define gen_helper_0e3i(name, arg1, arg2, arg3, arg4) do { \ #define gen_helper_0e3i(name, arg1, arg2, arg3, arg4) do { \
TCGv_i32 helper_tmp = tcg_const_i32(arg4); \ TCGv_i32 helper_tmp = tcg_const_i32(arg4); \
gen_helper_##name(cpu_env, arg1, arg2, arg3, helper_tmp); \ gen_helper_##name(cpu_env, arg1, arg2, arg3, helper_tmp); \
tcg_temp_free_i32(helper_tmp); \ tcg_temp_free_i32(helper_tmp); \
} while(0) } while (0)
typedef struct DisasContext { typedef struct DisasContext {
DisasContextBase base; DisasContextBase base;
@ -2661,7 +2661,7 @@ static inline void gen_load_srsgpr(int from, int to)
tcg_temp_free(t0); tcg_temp_free(t0);
} }
static inline void gen_store_srsgpr (int from, int to) static inline void gen_store_srsgpr(int from, int to)
{ {
if (to != 0) { if (to != 0) {
TCGv t0 = tcg_temp_new(); TCGv t0 = tcg_temp_new();
@ -3181,8 +3181,8 @@ static inline void check_eva(DisasContext *ctx)
static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \ static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \
int ft, int fs, int cc) \ int ft, int fs, int cc) \
{ \ { \
TCGv_i##bits fp0 = tcg_temp_new_i##bits (); \ TCGv_i##bits fp0 = tcg_temp_new_i##bits(); \
TCGv_i##bits fp1 = tcg_temp_new_i##bits (); \ TCGv_i##bits fp1 = tcg_temp_new_i##bits(); \
switch (ifmt) { \ switch (ifmt) { \
case FMT_PS: \ case FMT_PS: \
check_ps(ctx); \ check_ps(ctx); \
@ -3199,8 +3199,8 @@ static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \
} \ } \
break; \ break; \
} \ } \
gen_ldcmp_fpr##bits (ctx, fp0, fs); \ gen_ldcmp_fpr##bits(ctx, fp0, fs); \
gen_ldcmp_fpr##bits (ctx, fp1, ft); \ gen_ldcmp_fpr##bits(ctx, fp1, ft); \
switch (n) { \ switch (n) { \
case 0: \ case 0: \
gen_helper_0e2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); \ gen_helper_0e2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); \
@ -3253,8 +3253,8 @@ static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \
default: \ default: \
abort(); \ abort(); \
} \ } \
tcg_temp_free_i##bits (fp0); \ tcg_temp_free_i##bits(fp0); \
tcg_temp_free_i##bits (fp1); \ tcg_temp_free_i##bits(fp1); \
} }
FOP_CONDS(, 0, d, FMT_D, 64) FOP_CONDS(, 0, d, FMT_D, 64)
@ -3266,7 +3266,7 @@ FOP_CONDS(abs, 1, ps, FMT_PS, 64)
#undef FOP_CONDS #undef FOP_CONDS
#define FOP_CONDNS(fmt, ifmt, bits, STORE) \ #define FOP_CONDNS(fmt, ifmt, bits, STORE) \
static inline void gen_r6_cmp_ ## fmt(DisasContext * ctx, int n, \ static inline void gen_r6_cmp_ ## fmt(DisasContext *ctx, int n, \
int ft, int fs, int fd) \ int ft, int fs, int fd) \
{ \ { \
TCGv_i ## bits fp0 = tcg_temp_new_i ## bits(); \ TCGv_i ## bits fp0 = tcg_temp_new_i ## bits(); \
@ -3347,8 +3347,8 @@ static inline void gen_r6_cmp_ ## fmt(DisasContext * ctx, int n, \
abort(); \ abort(); \
} \ } \
STORE; \ STORE; \
tcg_temp_free_i ## bits (fp0); \ tcg_temp_free_i ## bits(fp0); \
tcg_temp_free_i ## bits (fp1); \ tcg_temp_free_i ## bits(fp1); \
} }
FOP_CONDNS(d, FMT_D, 64, gen_store_fpr64(ctx, fp0, fd)) FOP_CONDNS(d, FMT_D, 64, gen_store_fpr64(ctx, fp0, fd))
@ -3359,7 +3359,7 @@ FOP_CONDNS(s, FMT_S, 32, gen_store_fpr32(ctx, fp0, fd))
/* load/store instructions. */ /* load/store instructions. */
#ifdef CONFIG_USER_ONLY #ifdef CONFIG_USER_ONLY
#define OP_LD_ATOMIC(insn,fname) \ #define OP_LD_ATOMIC(insn, fname) \
static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
DisasContext *ctx) \ DisasContext *ctx) \
{ \ { \
@ -3371,16 +3371,16 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
tcg_temp_free(t0); \ tcg_temp_free(t0); \
} }
#else #else
#define OP_LD_ATOMIC(insn,fname) \ #define OP_LD_ATOMIC(insn, fname) \
static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
DisasContext *ctx) \ DisasContext *ctx) \
{ \ { \
gen_helper_1e1i(insn, ret, arg1, mem_idx); \ gen_helper_1e1i(insn, ret, arg1, mem_idx); \
} }
#endif #endif
OP_LD_ATOMIC(ll,ld32s); OP_LD_ATOMIC(ll, ld32s);
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
OP_LD_ATOMIC(lld,ld64); OP_LD_ATOMIC(lld, ld64);
#endif #endif
#undef OP_LD_ATOMIC #undef OP_LD_ATOMIC
@ -4227,7 +4227,10 @@ static void gen_arith(DisasContext *ctx, uint32_t opc,
tcg_temp_free(t2); tcg_temp_free(t2);
tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
tcg_temp_free(t1); tcg_temp_free(t1);
/* operands of different sign, first operand and result different sign */ /*
* Operands of different sign, first operand and result different
* sign.
*/
generate_exception(ctx, EXCP_OVERFLOW); generate_exception(ctx, EXCP_OVERFLOW);
gen_set_label(l1); gen_set_label(l1);
gen_store_gpr(t0, rd); gen_store_gpr(t0, rd);
@ -5777,7 +5780,7 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
} }
/* Traps */ /* Traps */
static void gen_trap (DisasContext *ctx, uint32_t opc, static void gen_trap(DisasContext *ctx, uint32_t opc,
int rs, int rt, int16_t imm) int rs, int rt, int16_t imm)
{ {
int cond; int cond;
@ -5900,7 +5903,7 @@ static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
} }
/* Branches (before delay slot) */ /* Branches (before delay slot) */
static void gen_compute_branch (DisasContext *ctx, uint32_t opc, static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
int insn_bytes, int insn_bytes,
int rs, int rt, int32_t offset, int rs, int rt, int32_t offset,
int delayslot_size) int delayslot_size)
@ -9731,7 +9734,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 7: case 7:
CP0_CHECK(ctx->kscrexist & (1 << sel)); CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_st_tl(arg, cpu_env, tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2])); offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
register_name = "KScratch"; register_name = "KScratch";
break; break;
default: default:
@ -9897,7 +9900,8 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
default: default:
gen_mfc0(ctx, t0, rt, sel); gen_mfc0(ctx, t0, rt, sel);
} }
} else switch (sel) { } else {
switch (sel) {
/* GPR registers. */ /* GPR registers. */
case 0: case 0:
gen_helper_1e0i(mftgpr, t0, rt); gen_helper_1e0i(mftgpr, t0, rt);
@ -9976,6 +9980,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
default: default:
goto die; goto die;
} }
}
trace_mips_translate_tr("mftr", rt, u, sel, h); trace_mips_translate_tr("mftr", rt, u, sel, h);
gen_store_gpr(t0, rd); gen_store_gpr(t0, rd);
tcg_temp_free(t0); tcg_temp_free(t0);
@ -10099,7 +10104,8 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
default: default:
gen_mtc0(ctx, t0, rd, sel); gen_mtc0(ctx, t0, rd, sel);
} }
} else switch (sel) { } else {
switch (sel) {
/* GPR registers. */ /* GPR registers. */
case 0: case 0:
gen_helper_0e1i(mttgpr, t0, rd); gen_helper_0e1i(mttgpr, t0, rd);
@ -10185,6 +10191,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
default: default:
goto die; goto die;
} }
}
trace_mips_translate_tr("mttr", rd, u, sel, h); trace_mips_translate_tr("mttr", rd, u, sel, h);
tcg_temp_free(t0); tcg_temp_free(t0);
return; return;
@ -10429,7 +10436,7 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
{ {
TCGv_i32 t1 = tcg_temp_new_i32(); TCGv_i32 t1 = tcg_temp_new_i32();
tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1));
tcg_gen_nand_i32(t0, t0, t1); tcg_gen_nand_i32(t0, t0, t1);
tcg_temp_free_i32(t1); tcg_temp_free_i32(t1);
tcg_gen_andi_i32(t0, t0, 1); tcg_gen_andi_i32(t0, t0, 1);
@ -10440,7 +10447,7 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
{ {
TCGv_i32 t1 = tcg_temp_new_i32(); TCGv_i32 t1 = tcg_temp_new_i32();
tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1));
tcg_gen_or_i32(t0, t0, t1); tcg_gen_or_i32(t0, t0, t1);
tcg_temp_free_i32(t1); tcg_temp_free_i32(t1);
tcg_gen_andi_i32(t0, t0, 1); tcg_gen_andi_i32(t0, t0, 1);
@ -10451,11 +10458,11 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
{ {
TCGv_i32 t1 = tcg_temp_new_i32(); TCGv_i32 t1 = tcg_temp_new_i32();
tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1));
tcg_gen_and_i32(t0, t0, t1); tcg_gen_and_i32(t0, t0, t1);
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2)); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 2));
tcg_gen_and_i32(t0, t0, t1); tcg_gen_and_i32(t0, t0, t1);
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3)); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 3));
tcg_gen_nand_i32(t0, t0, t1); tcg_gen_nand_i32(t0, t0, t1);
tcg_temp_free_i32(t1); tcg_temp_free_i32(t1);
tcg_gen_andi_i32(t0, t0, 1); tcg_gen_andi_i32(t0, t0, 1);
@ -10466,11 +10473,11 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
{ {
TCGv_i32 t1 = tcg_temp_new_i32(); TCGv_i32 t1 = tcg_temp_new_i32();
tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1));
tcg_gen_or_i32(t0, t0, t1); tcg_gen_or_i32(t0, t0, t1);
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2)); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 2));
tcg_gen_or_i32(t0, t0, t1); tcg_gen_or_i32(t0, t0, t1);
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3)); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 3));
tcg_gen_or_i32(t0, t0, t1); tcg_gen_or_i32(t0, t0, t1);
tcg_temp_free_i32(t1); tcg_temp_free_i32(t1);
tcg_gen_andi_i32(t0, t0, 1); tcg_gen_andi_i32(t0, t0, 1);
@ -10934,7 +10941,7 @@ static inline void gen_movcf_ps(DisasContext *ctx, int fs, int fd,
gen_store_fpr32(ctx, t0, fd); gen_store_fpr32(ctx, t0, fd);
gen_set_label(l1); gen_set_label(l1);
tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc+1)); tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc + 1));
tcg_gen_brcondi_i32(cond, t0, 0, l2); tcg_gen_brcondi_i32(cond, t0, 0, l2);
gen_load_fpr32h(ctx, t0, fs); gen_load_fpr32h(ctx, t0, fs);
gen_store_fpr32h(ctx, t0, fd); gen_store_fpr32h(ctx, t0, fd);
@ -11548,9 +11555,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
case OPC_CMP_NGT_S: case OPC_CMP_NGT_S:
check_insn_opc_removed(ctx, ISA_MIPS32R6); check_insn_opc_removed(ctx, ISA_MIPS32R6);
if (ctx->opcode & (1 << 6)) { if (ctx->opcode & (1 << 6)) {
gen_cmpabs_s(ctx, func-48, ft, fs, cc); gen_cmpabs_s(ctx, func - 48, ft, fs, cc);
} else { } else {
gen_cmp_s(ctx, func-48, ft, fs, cc); gen_cmp_s(ctx, func - 48, ft, fs, cc);
} }
break; break;
case OPC_ADD_D: case OPC_ADD_D:
@ -12030,9 +12037,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
case OPC_CMP_NGT_D: case OPC_CMP_NGT_D:
check_insn_opc_removed(ctx, ISA_MIPS32R6); check_insn_opc_removed(ctx, ISA_MIPS32R6);
if (ctx->opcode & (1 << 6)) { if (ctx->opcode & (1 << 6)) {
gen_cmpabs_d(ctx, func-48, ft, fs, cc); gen_cmpabs_d(ctx, func - 48, ft, fs, cc);
} else { } else {
gen_cmp_d(ctx, func-48, ft, fs, cc); gen_cmp_d(ctx, func - 48, ft, fs, cc);
} }
break; break;
case OPC_CVT_S_D: case OPC_CVT_S_D:
@ -12432,9 +12439,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
case OPC_CMP_LE_PS: case OPC_CMP_LE_PS:
case OPC_CMP_NGT_PS: case OPC_CMP_NGT_PS:
if (ctx->opcode & (1 << 6)) { if (ctx->opcode & (1 << 6)) {
gen_cmpabs_ps(ctx, func-48, ft, fs, cc); gen_cmpabs_ps(ctx, func - 48, ft, fs, cc);
} else { } else {
gen_cmp_ps(ctx, func-48, ft, fs, cc); gen_cmp_ps(ctx, func - 48, ft, fs, cc);
} }
break; break;
default: default:
@ -14247,7 +14254,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
case RR_RY_CNVT_SEH: case RR_RY_CNVT_SEH:
tcg_gen_ext16s_tl(cpu_gpr[rx], cpu_gpr[rx]); tcg_gen_ext16s_tl(cpu_gpr[rx], cpu_gpr[rx]);
break; break;
#if defined (TARGET_MIPS64) #if defined(TARGET_MIPS64)
case RR_RY_CNVT_ZEW: case RR_RY_CNVT_ZEW:
check_insn(ctx, ISA_MIPS64); check_insn(ctx, ISA_MIPS64);
check_mips_64(ctx); check_mips_64(ctx);
@ -14971,11 +14978,11 @@ static int mmreg2(int r)
/* Signed immediate */ /* Signed immediate */
#define SIMM(op, start, width) \ #define SIMM(op, start, width) \
((int32_t)(((op >> start) & ((~0U) >> (32-width))) \ ((int32_t)(((op >> start) & ((~0U) >> (32 - width))) \
<< (32-width)) \ << (32 - width)) \
>> (32-width)) >> (32 - width))
/* Zero-extended immediate */ /* Zero-extended immediate */
#define ZIMM(op, start, width) ((op >> start) & ((~0U) >> (32-width))) #define ZIMM(op, start, width) ((op >> start) & ((~0U) >> (32 - width)))
static void gen_addiur1sp(DisasContext *ctx) static void gen_addiur1sp(DisasContext *ctx)
{ {
@ -15669,7 +15676,10 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
save_cpu_state(ctx, 1); save_cpu_state(ctx, 1);
gen_helper_di(t0, cpu_env); gen_helper_di(t0, cpu_env);
gen_store_gpr(t0, rs); gen_store_gpr(t0, rs);
/* Stop translation as we may have switched the execution mode */ /*
* Stop translation as we may have switched the execution
* mode.
*/
ctx->base.is_jmp = DISAS_STOP; ctx->base.is_jmp = DISAS_STOP;
tcg_temp_free(t0); tcg_temp_free(t0);
} }
@ -15791,9 +15801,9 @@ static void gen_pool32fxf(DisasContext *ctx, int rt, int rs)
int extension = (ctx->opcode >> 6) & 0x3ff; int extension = (ctx->opcode >> 6) & 0x3ff;
uint32_t mips32_op; uint32_t mips32_op;
#define FLOAT_1BIT_FMT(opc, fmt) (fmt << 8) | opc #define FLOAT_1BIT_FMT(opc, fmt) ((fmt << 8) | opc)
#define FLOAT_2BIT_FMT(opc, fmt) (fmt << 7) | opc #define FLOAT_2BIT_FMT(opc, fmt) ((fmt << 7) | opc)
#define COND_FLOAT_MOV(opc, cond) (cond << 7) | opc #define COND_FLOAT_MOV(opc, cond) ((cond << 7) | opc)
switch (extension) { switch (extension) {
case FLOAT_1BIT_FMT(CFC1, 0): case FLOAT_1BIT_FMT(CFC1, 0):
@ -30128,7 +30138,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
translator_loop(&mips_tr_ops, &ctx.base, cs, tb, max_insns); translator_loop(&mips_tr_ops, &ctx.base, cs, tb, max_insns);
} }
static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags) static void fpu_dump_state(CPUMIPSState *env, FILE * f, int flags)
{ {
int i; int i;
int is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64); int is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64);
@ -30153,7 +30163,7 @@ static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags)
(double)tmp.fs[FP_ENDIAN_IDX], \ (double)tmp.fs[FP_ENDIAN_IDX], \
(double)tmp.fs[!FP_ENDIAN_IDX]); \ (double)tmp.fs[!FP_ENDIAN_IDX]); \
} \ } \
} while(0) } while (0)
qemu_fprintf(f, qemu_fprintf(f,
@ -30190,7 +30200,8 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
} }
} }
qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx "\n", qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x"
TARGET_FMT_lx "\n",
env->CP0_Status, env->CP0_Cause, env->CP0_EPC); env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016" qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016"
PRIx64 "\n", PRIx64 "\n",
@ -30211,7 +30222,8 @@ void mips_tcg_init(void)
cpu_gpr[0] = NULL; cpu_gpr[0] = NULL;
for (i = 1; i < 32; i++) for (i = 1; i < 32; i++)
cpu_gpr[i] = tcg_global_mem_new(cpu_env, cpu_gpr[i] = tcg_global_mem_new(cpu_env,
offsetof(CPUMIPSState, active_tc.gpr[i]), offsetof(CPUMIPSState,
active_tc.gpr[i]),
regnames[i]); regnames[i]);
for (i = 0; i < 32; i++) { for (i = 0; i < 32; i++) {
@ -30239,7 +30251,8 @@ void mips_tcg_init(void)
regnames_LO[i]); regnames_LO[i]);
} }
cpu_dspctrl = tcg_global_mem_new(cpu_env, cpu_dspctrl = tcg_global_mem_new(cpu_env,
offsetof(CPUMIPSState, active_tc.DSPControl), offsetof(CPUMIPSState,
active_tc.DSPControl),
"DSPControl"); "DSPControl");
bcond = tcg_global_mem_new(cpu_env, bcond = tcg_global_mem_new(cpu_env,
offsetof(CPUMIPSState, bcond), "bcond"); offsetof(CPUMIPSState, bcond), "bcond");