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target/hexagon: Remove hexagon_cpu_tlb_fill 

The fallback code in cpu_loop_exit_sigsegv is sufficient
for hexagon linux-user.

Remove the code from cpu_loop that raises SIGSEGV.

Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2021-09-14 16:32:17 -07:00
parent 5753605412
commit 70863887a8
2 changed files with 1 additions and 46 deletions
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24
linux-user/hexagon/cpu_loop.c
View File

@ -28,8 +28,7 @@
void cpu_loop(CPUHexagonState *env) void cpu_loop(CPUHexagonState *env)
{ {
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
int trapnr, signum, sigcode; int trapnr;
target_ulong sigaddr;
target_ulong syscallnum; target_ulong syscallnum;
target_ulong ret; target_ulong ret;
@ -39,10 +38,6 @@ void cpu_loop(CPUHexagonState *env)
cpu_exec_end(cs); cpu_exec_end(cs);
process_queued_cpu_work(cs); process_queued_cpu_work(cs);
signum = 0;
sigcode = 0;
sigaddr = 0;
switch (trapnr) { switch (trapnr) {
case EXCP_INTERRUPT: case EXCP_INTERRUPT:
/* just indicate that signals should be handled asap */ /* just indicate that signals should be handled asap */
@ -65,12 +60,6 @@ void cpu_loop(CPUHexagonState *env)
env->gpr[0] = ret; env->gpr[0] = ret;
} }
break; break;
case HEX_EXCP_FETCH_NO_UPAGE:
case HEX_EXCP_PRIV_NO_UREAD:
case HEX_EXCP_PRIV_NO_UWRITE:
signum = TARGET_SIGSEGV;
sigcode = TARGET_SEGV_MAPERR;
break;
case EXCP_ATOMIC: case EXCP_ATOMIC:
cpu_exec_step_atomic(cs); cpu_exec_step_atomic(cs);
break; break;
@ -79,17 +68,6 @@ void cpu_loop(CPUHexagonState *env)
trapnr); trapnr);
exit(EXIT_FAILURE); exit(EXIT_FAILURE);
} }
if (signum) {
target_siginfo_t info = {
.si_signo = signum,
.si_errno = 0,
.si_code = sigcode,
._sifields._sigfault._addr = sigaddr
};
queue_signal(env, info.si_signo, QEMU_SI_KILL, &info);
}
process_pending_signals(env); process_pending_signals(env);
} }
} }

23
target/hexagon/cpu.c
View File

@ -245,34 +245,11 @@ static void hexagon_cpu_init(Object *obj)
qdev_property_add_static(DEVICE(obj), &hexagon_lldb_stack_adjust_property); qdev_property_add_static(DEVICE(obj), &hexagon_lldb_stack_adjust_property);
} }
static bool hexagon_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
{
#ifdef CONFIG_USER_ONLY
switch (access_type) {
case MMU_INST_FETCH:
cs->exception_index = HEX_EXCP_FETCH_NO_UPAGE;
break;
case MMU_DATA_LOAD:
cs->exception_index = HEX_EXCP_PRIV_NO_UREAD;
break;
case MMU_DATA_STORE:
cs->exception_index = HEX_EXCP_PRIV_NO_UWRITE;
break;
}
cpu_loop_exit_restore(cs, retaddr);
#else
#error System mode not implemented for Hexagon
#endif
}
#include "hw/core/tcg-cpu-ops.h" #include "hw/core/tcg-cpu-ops.h"
static const struct TCGCPUOps hexagon_tcg_ops = { static const struct TCGCPUOps hexagon_tcg_ops = {
.initialize = hexagon_translate_init, .initialize = hexagon_translate_init,
.synchronize_from_tb = hexagon_cpu_synchronize_from_tb, .synchronize_from_tb = hexagon_cpu_synchronize_from_tb,
.tlb_fill = hexagon_tlb_fill,
}; };
static void hexagon_cpu_class_init(ObjectClass *c, void *data) static void hexagon_cpu_class_init(ObjectClass *c, void *data)