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docs/cxl: Change to lowercase as others 

Using the same style as elsewhere for topology / topo

Signed-off-by: Li Zhijian <lizhijian@cn.fujitsu.com>
Link: https://lore.kernel.org/r/20230519085802.2106900-2-lizhijian@cn.fujitsu.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
This commit is contained in:
Li Zhijian 2023-09-04 14:28:06 +01:00 committed by Michael Tokarev
parent acdc872d8a
commit 6ff359196d
1 changed files with 4 additions and 4 deletions
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8
docs/system/devices/cxl.rst
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@ -157,7 +157,7 @@ responsible for allocating appropriate ranges from within the CFMWs
and exposing those via normal memory configurations as would be done
for system RAM.
Example system Topology. x marks the match in each decoder level::
Example system topology. x marks the match in each decoder level::
|<------------------SYSTEM PHYSICAL ADDRESS MAP (1)----------------->|
| __________ __________________________________ __________ |
@ -187,8 +187,8 @@ Example system Topology. x marks the match in each decoder level::
___________|___ __________|__ __|_________ ___|_________
(3)| Root Port 0 | | Root Port 1 | | Root Port 2| | Root Port 3 |
| Appears in | | Appears in | | Appears in | | Appear in |
| PCI topology | | PCI Topology| | PCI Topo | | PCI Topo |
| As 0c:00.0 | | as 0c:01.0 | | as de:00.0 | | as de:01.0 |
| PCI topology | | PCI topology| | PCI topo | | PCI topo |
| as 0c:00.0 | | as 0c:01.0 | | as de:00.0 | | as de:01.0 |
|_______________| |_____________| |____________| |_____________|
| | | |
| | | |
@ -272,7 +272,7 @@ Example topology involving a switch::
| Root Port 0 |
| Appears in |
| PCI topology |
| As 0c:00.0 |
| as 0c:00.0 |
|___________x___|
|
|