mirror of https://github.com/xemu-project/xemu.git
target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg
henvcfg.PBMTE/STCE are read-only zero if menvcfg.PBMTE/STCE are zero. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230224040852.37109-3-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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@ -1956,7 +1956,11 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
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return ret;
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}
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*val = env->henvcfg;
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/*
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* henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
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* henvcfg.stce is read_only 0 when menvcfg.stce = 0
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*/
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*val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) | env->menvcfg);
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return RISCV_EXCP_NONE;
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}
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@ -1972,7 +1976,7 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
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}
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if (riscv_cpu_mxl(env) == MXL_RV64) {
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mask |= HENVCFG_PBMTE | HENVCFG_STCE;
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mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE);
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}
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env->henvcfg = (env->henvcfg & ~mask) | (val & mask);
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@ -1990,14 +1994,15 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
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return ret;
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}
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*val = env->henvcfg >> 32;
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*val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) |
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env->menvcfg)) >> 32;
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return RISCV_EXCP_NONE;
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}
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static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
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target_ulong val)
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{
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uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE;
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uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE);
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uint64_t valh = (uint64_t)val << 32;
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RISCVException ret;
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