mirror of https://github.com/xemu-project/xemu.git
import hatari dsp
This commit is contained in:
espes
parent
4bb3043bf5
commit
6f22e7679b
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@ -0,0 +1,799 @@
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/*
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DSP M56001 emulation
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Dummy emulation, Hatari glue
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(C) 2001-2008 ARAnyM developer team
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Adaption to Hatari (C) 2008 by Thomas Huth
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <ctype.h>
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#include "main.h"
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#include "sysdeps.h"
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#include "newcpu.h"
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#include "memorySnapShot.h"
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#include "ioMem.h"
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#include "dsp.h"
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#include "crossbar.h"
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#include "configuration.h"
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#include "cycInt.h"
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#include "m68000.h"
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#if ENABLE_DSP_EMU
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#include "debugdsp.h"
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#include "dsp_cpu.h"
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#include "dsp_disasm.h"
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#endif
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#define DEBUG 0
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#if DEBUG
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#define Dprintf(a) printf a
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#else
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#define Dprintf(a)
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#endif
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#define DSP_HW_OFFSET 0xFFA200
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#if ENABLE_DSP_EMU
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static const char* x_ext_memory_addr_name[] = {
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"", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
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"PBC", "PCC", "PBDDR", "PCDDR", "PBD", "PCD", "", "",
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"HCR", "HSR", "", "HRX/HTX", "CRA", "CRB", "SSISR/TSR", "RX/TX",
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"SCR", "SSR", "SCCR", "STXA", "SRX/STX", "SRX/STX", "SRX/STX", "",
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"", "", "", "", "", "", "BCR", "IPR"
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};
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static Sint32 save_cycles;
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#endif
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static bool bDspDebugging;
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bool bDspEnabled = false;
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bool bDspHostInterruptPending = false;
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/**
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* Trigger HREQ interrupt at the host CPU.
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*/
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#if ENABLE_DSP_EMU
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static void DSP_TriggerHostInterrupt(void)
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{
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bDspHostInterruptPending = true;
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M68000_SetSpecial(SPCFLAG_DSP);
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}
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#endif
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/**
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* This function is called from the CPU emulation part when SPCFLAG_DSP is set.
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* If the DSP's IRQ signal is set, we check that SR allows a level 6 interrupt,
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* and if so, we call M68000_Exception.
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*/
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#if ENABLE_DSP_EMU
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bool DSP_ProcessIRQ(void)
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{
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if (bDspHostInterruptPending && regs.intmask < 6)
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{
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M68000_Exception(IoMem_ReadByte(0xffa203)*4, M68000_EXC_SRC_INT_DSP);
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bDspHostInterruptPending = false;
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M68000_UnsetSpecial(SPCFLAG_DSP);
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return true;
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}
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return false;
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}
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#endif
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/**
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* Initialize the DSP emulation
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*/
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void DSP_Init(void)
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{
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#if ENABLE_DSP_EMU
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if (bDspEnabled || ConfigureParams.System.nDSPType != DSP_TYPE_EMU)
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return;
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dsp_core_init(DSP_TriggerHostInterrupt);
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dsp56k_init_cpu();
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bDspEnabled = true;
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save_cycles = 0;
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#endif
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}
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/**
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* Shut down the DSP emulation
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*/
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void DSP_UnInit(void)
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{
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#if ENABLE_DSP_EMU
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if (!bDspEnabled)
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return;
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dsp_core_shutdown();
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bDspEnabled = false;
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#endif
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}
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/**
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* Reset the DSP emulation
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*/
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void DSP_Reset(void)
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{
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#if ENABLE_DSP_EMU
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dsp_core_reset();
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bDspHostInterruptPending = false;
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save_cycles = 0;
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#endif
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}
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/**
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* Save/Restore snapshot of CPU variables ('MemorySnapShot_Store' handles type)
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*/
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void DSP_MemorySnapShot_Capture(bool bSave)
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{
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#if ENABLE_DSP_EMU
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if (!bSave)
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DSP_Reset();
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MemorySnapShot_Store(&bDspEnabled, sizeof(bDspEnabled));
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MemorySnapShot_Store(&dsp_core, sizeof(dsp_core));
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MemorySnapShot_Store(&save_cycles, sizeof(save_cycles));
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#endif
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}
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/**
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* Run DSP for certain cycles
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*/
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void DSP_Run(int nHostCycles)
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{
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#if ENABLE_DSP_EMU
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save_cycles += nHostCycles * 2;
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if (dsp_core.running == 0)
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return;
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if (save_cycles <= 0)
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return;
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if (unlikely(bDspDebugging)) {
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while (save_cycles > 0)
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{
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dsp56k_execute_instruction();
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save_cycles -= dsp_core.instr_cycle;
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DebugDsp_Check();
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}
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} else {
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// fprintf(stderr, "--> %d\n", save_cycles);
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while (save_cycles > 0)
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{
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dsp56k_execute_instruction();
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save_cycles -= dsp_core.instr_cycle;
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}
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}
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#endif
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}
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/**
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* Enable/disable DSP debugging mode
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*/
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void DSP_SetDebugging(bool enabled)
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{
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bDspDebugging = enabled;
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}
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/**
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* Get DSP program counter (for debugging)
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*/
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Uint16 DSP_GetPC(void)
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{
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#if ENABLE_DSP_EMU
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if (bDspEnabled)
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return dsp_core.pc;
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else
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#endif
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return 0;
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}
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/**
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* Get next DSP PC without output (for debugging)
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*/
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Uint16 DSP_GetNextPC(Uint16 pc)
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{
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#if ENABLE_DSP_EMU
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/* code is reduced copy from dsp56k_execute_one_disasm_instruction() */
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dsp_core_t dsp_core_save;
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Uint16 instruction_length;
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if (!bDspEnabled)
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return 0;
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/* Save DSP context */
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memcpy(&dsp_core_save, &dsp_core, sizeof(dsp_core));
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/* Disasm instruction */
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dsp_core.pc = pc;
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/* why dsp56k_execute_one_disasm_instruction() does "-1"
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* for this value, that doesn't seem right???
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*/
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instruction_length = dsp56k_disasm(DSP_DISASM_MODE);
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/* Restore DSP context */
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memcpy(&dsp_core, &dsp_core_save, sizeof(dsp_core));
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return pc + instruction_length;
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#else
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return 0;
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#endif
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}
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/**
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* Get current DSP instruction cycles (for profiling)
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*/
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Uint16 DSP_GetInstrCycles(void)
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{
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#if ENABLE_DSP_EMU
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if (bDspEnabled)
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return dsp_core.instr_cycle;
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else
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#endif
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return 0;
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}
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/**
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* Disassemble DSP code between given addresses, return next PC address
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*/
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Uint16 DSP_DisasmAddress(FILE *out, Uint16 lowerAdr, Uint16 UpperAdr)
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{
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#if ENABLE_DSP_EMU
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Uint16 dsp_pc;
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for (dsp_pc=lowerAdr; dsp_pc<=UpperAdr; dsp_pc++) {
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dsp_pc += dsp56k_execute_one_disasm_instruction(out, dsp_pc);
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}
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return dsp_pc;
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#else
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return 0;
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#endif
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}
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/**
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* Get the value from the given (16-bit) DSP memory address / space
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* exactly the same way as in dsp_cpu.c::read_memory() (except for
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* the host/transmit peripheral register values which access has
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* side-effects). Set the mem_str to suitable string for that
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* address / space.
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* Return the value at given address. For valid values AND the return
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* value with BITMASK(24).
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*/
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Uint32 DSP_ReadMemory(Uint16 address, char space_id, const char **mem_str)
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{
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#if ENABLE_DSP_EMU
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static const char *spaces[3][4] = {
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{ "X ram", "X rom", "X", "X periph" },
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{ "Y ram", "Y rom", "Y", "Y periph" },
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{ "P ram", "P ram", "P ext memory", "P ext memory" }
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};
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int idx, space;
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switch (space_id) {
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case 'X':
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space = DSP_SPACE_X;
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idx = 0;
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break;
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case 'Y':
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space = DSP_SPACE_Y;
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idx = 1;
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break;
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case 'P':
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space = DSP_SPACE_P;
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idx = 2;
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break;
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default:
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space = DSP_SPACE_X;
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idx = 0;
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}
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address &= 0xFFFF;
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/* Internal RAM ? */
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if (address < 0x100) {
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*mem_str = spaces[idx][0];
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return dsp_core.ramint[space][address];
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}
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if (space == DSP_SPACE_P) {
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/* Internal RAM ? */
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if (address < 0x200) {
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*mem_str = spaces[idx][0];
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return dsp_core.ramint[DSP_SPACE_P][address];
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}
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/* External RAM, mask address to available ram size */
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*mem_str = spaces[idx][2];
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return dsp_core.ramext[address & (DSP_RAMSIZE-1)];
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}
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/* Internal ROM ? */
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if (address < 0x200) {
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if (dsp_core.registers[DSP_REG_OMR] & (1<<DSP_OMR_DE)) {
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*mem_str = spaces[idx][1];
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return dsp_core.rom[space][address];
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}
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}
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/* Peripheral address ? */
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if (address >= 0xffc0) {
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*mem_str = spaces[idx][3];
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/* reading host/transmit regs has side-effects,
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* so just give the memory value.
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*/
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return dsp_core.periph[space][address-0xffc0];
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}
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/* Falcon: External RAM, map X to upper 16K of matching space in Y,P */
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address &= (DSP_RAMSIZE>>1) - 1;
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if (space == DSP_SPACE_X) {
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address += DSP_RAMSIZE>>1;
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}
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/* Falcon: External RAM, finally map X,Y to P */
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*mem_str = spaces[idx][2];
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return dsp_core.ramext[address & (DSP_RAMSIZE-1)];
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#endif
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return 0;
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}
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/**
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* Output memory values between given addresses in given DSP address space.
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* Return next DSP address value.
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*/
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Uint16 DSP_DisasmMemory(Uint16 dsp_memdump_addr, Uint16 dsp_memdump_upper, char space)
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{
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#if ENABLE_DSP_EMU
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Uint32 mem, mem2, value;
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const char *mem_str;
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for (mem = dsp_memdump_addr; mem <= dsp_memdump_upper; mem++) {
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/* special printing of host communication/transmit registers */
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if (space == 'X' && mem >= 0xffc0) {
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if (mem == 0xffeb) {
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fprintf(stderr,"X periph:%04x HTX : %06x RTX:%06x\n",
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mem, dsp_core.dsp_host_htx, dsp_core.dsp_host_rtx);
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}
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else if (mem == 0xffef) {
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fprintf(stderr,"X periph:%04x SSI TX : %06x SSI RX:%06x\n",
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mem, dsp_core.ssi.transmit_value, dsp_core.ssi.received_value);
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}
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else {
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value = DSP_ReadMemory(mem, space, &mem_str);
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fprintf(stderr,"%s:%04x %06x\t%s\n", mem_str, mem, value, x_ext_memory_addr_name[mem-0xffc0]);
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}
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continue;
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}
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/* special printing of X & Y external RAM values */
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if ((space == 'X' || space == 'Y') &&
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mem >= 0x200 && mem < 0xffc0) {
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mem2 = mem & ((DSP_RAMSIZE>>1)-1);
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if (space == 'X') {
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mem2 += (DSP_RAMSIZE>>1);
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}
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fprintf(stderr,"%c:%04x (P:%04x): %06x\n", space,
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mem, mem2, dsp_core.ramext[mem2 & (DSP_RAMSIZE-1)]);
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continue;
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}
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value = DSP_ReadMemory(mem, space, &mem_str);
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fprintf(stderr,"%s:%04x %06x\n", mem_str, mem, value);
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}
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#endif
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return dsp_memdump_upper+1;
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}
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/**
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* Show information on DSP core state which isn't
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* shown by any of the other commands (dd, dm, dr).
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*/
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void DSP_Info(Uint32 dummy)
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{
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#if ENABLE_DSP_EMU
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int i, j;
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const char *stackname[] = { "SSH", "SSL" };
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fputs("DSP core information:\n", stderr);
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for (i = 0; i < ARRAYSIZE(stackname); i++) {
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fprintf(stderr, "- %s stack:", stackname[i]);
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for (j = 0; j < ARRAYSIZE(dsp_core.stack[0]); j++) {
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fprintf(stderr, " %04hx", dsp_core.stack[i][j]);
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}
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fputs("\n", stderr);
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}
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fprintf(stderr, "- Interrupt IPL:");
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for (i = 0; i < ARRAYSIZE(dsp_core.interrupt_ipl); i++) {
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fprintf(stderr, " %04hx", dsp_core.interrupt_ipl[i]);
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}
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fputs("\n", stderr);
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fprintf(stderr, "- Pending ints: ");
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for (i = 0; i < ARRAYSIZE(dsp_core.interrupt_isPending); i++) {
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fprintf(stderr, " %04hx", dsp_core.interrupt_isPending[i]);
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}
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fputs("\n", stderr);
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fprintf(stderr, "- Hostport:");
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for (i = 0; i < ARRAYSIZE(dsp_core.hostport); i++) {
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fprintf(stderr, " %02x", dsp_core.hostport[i]);
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}
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fputs("\n", stderr);
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#endif
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}
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/**
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* Show DSP register contents
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*/
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void DSP_DisasmRegisters(void)
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{
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#if ENABLE_DSP_EMU
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Uint32 i;
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fprintf(stderr,"A: A2: %02x A1: %06x A0: %06x\n",
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dsp_core.registers[DSP_REG_A2], dsp_core.registers[DSP_REG_A1], dsp_core.registers[DSP_REG_A0]);
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fprintf(stderr,"B: B2: %02x B1: %06x B0: %06x\n",
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dsp_core.registers[DSP_REG_B2], dsp_core.registers[DSP_REG_B1], dsp_core.registers[DSP_REG_B0]);
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fprintf(stderr,"X: X1: %06x X0: %06x\n", dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0]);
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fprintf(stderr,"Y: Y1: %06x Y0: %06x\n", dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0]);
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for (i=0; i<8; i++) {
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fprintf(stderr,"R%01x: %04x N%01x: %04x M%01x: %04x\n",
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i, dsp_core.registers[DSP_REG_R0+i],
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i, dsp_core.registers[DSP_REG_N0+i],
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i, dsp_core.registers[DSP_REG_M0+i]);
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}
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fprintf(stderr,"LA: %04x LC: %04x PC: %04x\n", dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], dsp_core.pc);
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fprintf(stderr,"SR: %04x OMR: %02x\n", dsp_core.registers[DSP_REG_SR], dsp_core.registers[DSP_REG_OMR]);
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fprintf(stderr,"SP: %02x SSH: %04x SSL: %04x\n",
|
||||
dsp_core.registers[DSP_REG_SP], dsp_core.registers[DSP_REG_SSH], dsp_core.registers[DSP_REG_SSL]);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Get given DSP register address and required bit mask.
|
||||
* Works for A0-2, B0-2, LA, LC, M0-7, N0-7, R0-7, X0-1, Y0-1, PC, SR, SP,
|
||||
* OMR, SSH & SSL registers, but note that the SP, SSH & SSL registers
|
||||
* need special handling (in DSP*SetRegister()) when they are set.
|
||||
* Return the register width in bits or zero for an error.
|
||||
*/
|
||||
int DSP_GetRegisterAddress(const char *regname, Uint32 **addr, Uint32 *mask)
|
||||
{
|
||||
#if ENABLE_DSP_EMU
|
||||
#define MAX_REGNAME_LEN 4
|
||||
typedef struct {
|
||||
const char name[MAX_REGNAME_LEN];
|
||||
Uint32 *addr;
|
||||
size_t bits;
|
||||
Uint32 mask;
|
||||
} reg_addr_t;
|
||||
|
||||
/* sorted by name so that this can be bisected */
|
||||
static const reg_addr_t registers[] = {
|
||||
|
||||
/* 56-bit A register */
|
||||
{ "A0", &dsp_core.registers[DSP_REG_A0], 32, BITMASK(24) },
|
||||
{ "A1", &dsp_core.registers[DSP_REG_A1], 32, BITMASK(24) },
|
||||
{ "A2", &dsp_core.registers[DSP_REG_A2], 32, BITMASK(8) },
|
||||
|
||||
/* 56-bit B register */
|
||||
{ "B0", &dsp_core.registers[DSP_REG_B0], 32, BITMASK(24) },
|
||||
{ "B1", &dsp_core.registers[DSP_REG_B1], 32, BITMASK(24) },
|
||||
{ "B2", &dsp_core.registers[DSP_REG_B2], 32, BITMASK(8) },
|
||||
|
||||
/* 16-bit LA & LC registers */
|
||||
{ "LA", &dsp_core.registers[DSP_REG_LA], 32, BITMASK(16) },
|
||||
{ "LC", &dsp_core.registers[DSP_REG_LC], 32, BITMASK(16) },
|
||||
|
||||
/* 16-bit M registers */
|
||||
{ "M0", &dsp_core.registers[DSP_REG_M0], 32, BITMASK(16) },
|
||||
{ "M1", &dsp_core.registers[DSP_REG_M1], 32, BITMASK(16) },
|
||||
{ "M2", &dsp_core.registers[DSP_REG_M2], 32, BITMASK(16) },
|
||||
{ "M3", &dsp_core.registers[DSP_REG_M3], 32, BITMASK(16) },
|
||||
{ "M4", &dsp_core.registers[DSP_REG_M4], 32, BITMASK(16) },
|
||||
{ "M5", &dsp_core.registers[DSP_REG_M5], 32, BITMASK(16) },
|
||||
{ "M6", &dsp_core.registers[DSP_REG_M6], 32, BITMASK(16) },
|
||||
{ "M7", &dsp_core.registers[DSP_REG_M7], 32, BITMASK(16) },
|
||||
|
||||
/* 16-bit N registers */
|
||||
{ "N0", &dsp_core.registers[DSP_REG_N0], 32, BITMASK(16) },
|
||||
{ "N1", &dsp_core.registers[DSP_REG_N1], 32, BITMASK(16) },
|
||||
{ "N2", &dsp_core.registers[DSP_REG_N2], 32, BITMASK(16) },
|
||||
{ "N3", &dsp_core.registers[DSP_REG_N3], 32, BITMASK(16) },
|
||||
{ "N4", &dsp_core.registers[DSP_REG_N4], 32, BITMASK(16) },
|
||||
{ "N5", &dsp_core.registers[DSP_REG_N5], 32, BITMASK(16) },
|
||||
{ "N6", &dsp_core.registers[DSP_REG_N6], 32, BITMASK(16) },
|
||||
{ "N7", &dsp_core.registers[DSP_REG_N7], 32, BITMASK(16) },
|
||||
|
||||
{ "OMR", &dsp_core.registers[DSP_REG_OMR], 32, 0x5f },
|
||||
|
||||
/* 16-bit program counter */
|
||||
{ "PC", (Uint32*)(&dsp_core.pc), 16, BITMASK(16) },
|
||||
|
||||
/* 16-bit DSP R (address) registers */
|
||||
{ "R0", &dsp_core.registers[DSP_REG_R0], 32, BITMASK(16) },
|
||||
{ "R1", &dsp_core.registers[DSP_REG_R1], 32, BITMASK(16) },
|
||||
{ "R2", &dsp_core.registers[DSP_REG_R2], 32, BITMASK(16) },
|
||||
{ "R3", &dsp_core.registers[DSP_REG_R3], 32, BITMASK(16) },
|
||||
{ "R4", &dsp_core.registers[DSP_REG_R4], 32, BITMASK(16) },
|
||||
{ "R5", &dsp_core.registers[DSP_REG_R5], 32, BITMASK(16) },
|
||||
{ "R6", &dsp_core.registers[DSP_REG_R6], 32, BITMASK(16) },
|
||||
{ "R7", &dsp_core.registers[DSP_REG_R7], 32, BITMASK(16) },
|
||||
|
||||
{ "SSH", &dsp_core.registers[DSP_REG_SSH], 32, BITMASK(16) },
|
||||
{ "SSL", &dsp_core.registers[DSP_REG_SSL], 32, BITMASK(16) },
|
||||
{ "SP", &dsp_core.registers[DSP_REG_SP], 32, BITMASK(6) },
|
||||
|
||||
/* 16-bit status register */
|
||||
{ "SR", &dsp_core.registers[DSP_REG_SR], 32, 0xefff },
|
||||
|
||||
/* 48-bit X register */
|
||||
{ "X0", &dsp_core.registers[DSP_REG_X0], 32, BITMASK(24) },
|
||||
{ "X1", &dsp_core.registers[DSP_REG_X1], 32, BITMASK(24) },
|
||||
|
||||
/* 48-bit Y register */
|
||||
{ "Y0", &dsp_core.registers[DSP_REG_Y0], 32, BITMASK(24) },
|
||||
{ "Y1", &dsp_core.registers[DSP_REG_Y1], 32, BITMASK(24) }
|
||||
};
|
||||
/* left, right, middle, direction */
|
||||
int l, r, m, dir = 0;
|
||||
unsigned int i, len;
|
||||
char reg[MAX_REGNAME_LEN];
|
||||
|
||||
if (!bDspEnabled) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
for (i = 0; i < sizeof(reg) && regname[i]; i++) {
|
||||
reg[i] = toupper(regname[i]);
|
||||
}
|
||||
if (i < 2 || regname[i]) {
|
||||
/* too short or longer than any of the names */
|
||||
return 0;
|
||||
}
|
||||
len = i;
|
||||
|
||||
/* bisect */
|
||||
l = 0;
|
||||
r = ARRAYSIZE(registers) - 1;
|
||||
do {
|
||||
m = (l+r) >> 1;
|
||||
for (i = 0; i < len; i++) {
|
||||
dir = (int)reg[i] - registers[m].name[i];
|
||||
if (dir) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (dir == 0) {
|
||||
*addr = registers[m].addr;
|
||||
*mask = registers[m].mask;
|
||||
return registers[m].bits;
|
||||
}
|
||||
if (dir < 0) {
|
||||
r = m-1;
|
||||
} else {
|
||||
l = m+1;
|
||||
}
|
||||
} while (l <= r);
|
||||
#undef MAX_REGNAME_LEN
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Set given DSP register value, return false if unknown register given
|
||||
*/
|
||||
bool DSP_Disasm_SetRegister(const char *arg, Uint32 value)
|
||||
{
|
||||
#if ENABLE_DSP_EMU
|
||||
Uint32 *addr, mask, sp_value;
|
||||
int bits;
|
||||
|
||||
/* first check registers needing special handling... */
|
||||
if (arg[0]=='S' || arg[0]=='s') {
|
||||
if (arg[1]=='P' || arg[1]=='p') {
|
||||
dsp_core.registers[DSP_REG_SP] = value & BITMASK(6);
|
||||
value &= BITMASK(4);
|
||||
dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][value];
|
||||
dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][value];
|
||||
return true;
|
||||
}
|
||||
if (arg[1]=='S' || arg[1]=='s') {
|
||||
sp_value = dsp_core.registers[DSP_REG_SP] & BITMASK(4);
|
||||
if (arg[2]=='H' || arg[2]=='h') {
|
||||
if (sp_value == 0) {
|
||||
dsp_core.registers[DSP_REG_SSH] = 0;
|
||||
dsp_core.stack[0][sp_value] = 0;
|
||||
} else {
|
||||
dsp_core.registers[DSP_REG_SSH] = value & BITMASK(16);
|
||||
dsp_core.stack[0][sp_value] = value & BITMASK(16);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
if (arg[2]=='L' || arg[2]=='l') {
|
||||
if (sp_value == 0) {
|
||||
dsp_core.registers[DSP_REG_SSL] = 0;
|
||||
dsp_core.stack[1][sp_value] = 0;
|
||||
} else {
|
||||
dsp_core.registers[DSP_REG_SSL] = value & BITMASK(16);
|
||||
dsp_core.stack[1][sp_value] = value & BITMASK(16);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* ...then registers where address & mask are enough */
|
||||
bits = DSP_GetRegisterAddress(arg, &addr, &mask);
|
||||
switch (bits) {
|
||||
case 32:
|
||||
*addr = value & mask;
|
||||
return true;
|
||||
case 16:
|
||||
*(Uint16*)addr = value & mask;
|
||||
return true;
|
||||
}
|
||||
#endif
|
||||
return false;
|
||||
}
|
||||
|
||||
/**
|
||||
* Read SSI transmit value
|
||||
*/
|
||||
Uint32 DSP_SsiReadTxValue(void)
|
||||
{
|
||||
#if ENABLE_DSP_EMU
|
||||
return dsp_core.ssi.transmit_value;
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* Write SSI receive value
|
||||
*/
|
||||
void DSP_SsiWriteRxValue(Uint32 value)
|
||||
{
|
||||
#if ENABLE_DSP_EMU
|
||||
dsp_core.ssi.received_value = value & 0xffffff;
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* Signal SSI clock tick to DSP
|
||||
*/
|
||||
|
||||
void DSP_SsiReceive_SC0(void)
|
||||
{
|
||||
#if ENABLE_DSP_EMU
|
||||
dsp_core_ssi_Receive_SC0();
|
||||
#endif
|
||||
}
|
||||
|
||||
void DSP_SsiTransmit_SC0(void)
|
||||
{
|
||||
#if ENABLE_DSP_EMU
|
||||
#endif
|
||||
}
|
||||
|
||||
void DSP_SsiReceive_SC1(Uint32 FrameCounter)
|
||||
{
|
||||
#if ENABLE_DSP_EMU
|
||||
dsp_core_ssi_Receive_SC1(FrameCounter);
|
||||
#endif
|
||||
}
|
||||
|
||||
void DSP_SsiTransmit_SC1(void)
|
||||
{
|
||||
#if ENABLE_DSP_EMU
|
||||
Crossbar_DmaPlayInHandShakeMode();
|
||||
#endif
|
||||
}
|
||||
|
||||
void DSP_SsiReceive_SC2(Uint32 FrameCounter)
|
||||
{
|
||||
#if ENABLE_DSP_EMU
|
||||
dsp_core_ssi_Receive_SC2(FrameCounter);
|
||||
#endif
|
||||
}
|
||||
|
||||
void DSP_SsiTransmit_SC2(Uint32 frame)
|
||||
{
|
||||
#if ENABLE_DSP_EMU
|
||||
Crossbar_DmaRecordInHandShakeMode_Frame(frame);
|
||||
#endif
|
||||
}
|
||||
|
||||
void DSP_SsiReceive_SCK(void)
|
||||
{
|
||||
#if ENABLE_DSP_EMU
|
||||
dsp_core_ssi_Receive_SCK();
|
||||
#endif
|
||||
}
|
||||
|
||||
void DSP_SsiTransmit_SCK(void)
|
||||
{
|
||||
#if ENABLE_DSP_EMU
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* Read access wrapper for ioMemTabFalcon (DSP Host port)
|
||||
* DSP Host interface port is accessed by the 68030 in Byte mode.
|
||||
* A move.w value,$ffA206 results in 2 bus access for the 68030.
|
||||
*/
|
||||
void DSP_HandleReadAccess(void)
|
||||
{
|
||||
Uint32 addr;
|
||||
Uint8 value;
|
||||
bool multi_access = false;
|
||||
|
||||
for (addr = IoAccessBaseAddress; addr < IoAccessBaseAddress+nIoMemAccessSize; addr++)
|
||||
{
|
||||
#if ENABLE_DSP_EMU
|
||||
value = dsp_core_read_host(addr-DSP_HW_OFFSET);
|
||||
#else
|
||||
/* this value prevents TOS from hanging in the DSP init code */
|
||||
value = 0xff;
|
||||
#endif
|
||||
if (multi_access == true)
|
||||
M68000_AddCycles(4);
|
||||
multi_access = true;
|
||||
|
||||
Dprintf(("HWget_b(0x%08x)=0x%02x at 0x%08x\n", addr, value, m68k_getpc()));
|
||||
IoMem_WriteByte(addr, value);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Write access wrapper for ioMemTabFalcon (DSP Host port)
|
||||
* DSP Host interface port is accessed by the 68030 in Byte mode.
|
||||
* A move.w value,$ffA206 results in 2 bus access for the 68030.
|
||||
*/
|
||||
void DSP_HandleWriteAccess(void)
|
||||
{
|
||||
Uint32 addr;
|
||||
bool multi_access = false;
|
||||
|
||||
for (addr = IoAccessBaseAddress; addr < IoAccessBaseAddress+nIoMemAccessSize; addr++)
|
||||
{
|
||||
#if ENABLE_DSP_EMU
|
||||
Uint8 value = IoMem_ReadByte(addr);
|
||||
Dprintf(("HWput_b(0x%08x,0x%02x) at 0x%08x\n", addr, value, m68k_getpc()));
|
||||
dsp_core_write_host(addr-DSP_HW_OFFSET, value);
|
||||
#endif
|
||||
if (multi_access == true)
|
||||
M68000_AddCycles(4);
|
||||
multi_access = true;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
/*
|
||||
DSP M56001 emulation
|
||||
Dummy emulation, Hatari glue
|
||||
|
||||
(C) 2001-2008 ARAnyM developer team
|
||||
Adaption to Hatari (C) 2008 by Thomas Huth
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef DSP_H
|
||||
#define DSP_H
|
||||
|
||||
#if ENABLE_DSP_EMU
|
||||
# include "dsp_core.h"
|
||||
#endif
|
||||
|
||||
#define DSP_FREQ (CPU_FREQ*4)
|
||||
|
||||
extern bool bDspEnabled;
|
||||
extern bool bDspHostInterruptPending;
|
||||
|
||||
/* Dsp commands */
|
||||
extern bool DSP_ProcessIRQ(void);
|
||||
extern void DSP_Init(void);
|
||||
extern void DSP_UnInit(void);
|
||||
extern void DSP_Reset(void);
|
||||
extern void DSP_Run(int nHostCycles);
|
||||
|
||||
/* Save Dsp state to snapshot */
|
||||
extern void DSP_MemorySnapShot_Capture(bool bSave);
|
||||
|
||||
/* Dsp Debugger commands */
|
||||
extern void DSP_SetDebugging(bool enabled);
|
||||
extern Uint16 DSP_GetPC(void);
|
||||
extern Uint16 DSP_GetNextPC(Uint16 pc);
|
||||
extern Uint16 DSP_GetInstrCycles(void);
|
||||
extern Uint32 DSP_ReadMemory(Uint16 addr, char space, const char **mem_str);
|
||||
extern Uint16 DSP_DisasmMemory(Uint16 dsp_memdump_addr, Uint16 dsp_memdump_upper, char space);
|
||||
extern Uint16 DSP_DisasmAddress(FILE *out, Uint16 lowerAdr, Uint16 UpperAdr);
|
||||
extern void DSP_Info(Uint32 dummy);
|
||||
extern void DSP_DisasmRegisters(void);
|
||||
extern int DSP_GetRegisterAddress(const char *arg, Uint32 **addr, Uint32 *mask);
|
||||
extern bool DSP_Disasm_SetRegister(const char *arg, Uint32 value);
|
||||
|
||||
/* Dsp SSI commands */
|
||||
extern Uint32 DSP_SsiReadTxValue(void);
|
||||
extern void DSP_SsiWriteRxValue(Uint32 value);
|
||||
extern void DSP_SsiReceive_SC0(void);
|
||||
extern void DSP_SsiReceive_SC1(Uint32 value);
|
||||
extern void DSP_SsiReceive_SC2(Uint32 value);
|
||||
extern void DSP_SsiReceive_SCK(void);
|
||||
extern void DSP_SsiTransmit_SC0(void);
|
||||
extern void DSP_SsiTransmit_SC1(void);
|
||||
extern void DSP_SsiTransmit_SC2(Uint32 frame);
|
||||
extern void DSP_SsiTransmit_SCK(void);
|
||||
|
||||
|
||||
/* Dsp Host interface commands */
|
||||
extern void DSP_HandleReadAccess(void);
|
||||
extern void DSP_HandleWriteAccess(void);
|
||||
extern Uint16 DSP_Get_HREQ(void);
|
||||
|
||||
|
||||
#endif /* DSP_H */
|
||||
|
|
@ -0,0 +1,704 @@
|
|||
/*
|
||||
DSP M56001 emulation
|
||||
Host/Emulator <-> DSP glue
|
||||
|
||||
(C) 2003-2008 ARAnyM developer team
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifdef HAVE_CONFIG_H
|
||||
#include "config.h"
|
||||
#endif
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
|
||||
#include "dsp_core.h"
|
||||
#include "dsp_cpu.h"
|
||||
#include "ioMem.h"
|
||||
#include "dsp.h"
|
||||
#include "log.h"
|
||||
|
||||
/*--- the DSP core itself ---*/
|
||||
dsp_core_t dsp_core;
|
||||
|
||||
/*--- Defines ---*/
|
||||
#ifndef M_PI
|
||||
#define M_PI 3.141592653589793238462643383279502
|
||||
#endif
|
||||
|
||||
/*--- Functions prototypes ---*/
|
||||
static void dsp_core_dsp2host(void);
|
||||
static void dsp_core_host2dsp(void);
|
||||
|
||||
static void (*dsp_host_interrupt)(void); /* Function to trigger host interrupt */
|
||||
|
||||
/* Init DSP emulation */
|
||||
void dsp_core_init(void (*host_interrupt)(void))
|
||||
{
|
||||
int i;
|
||||
|
||||
LOG_TRACE(TRACE_DSP_STATE, "Dsp: core init\n");
|
||||
|
||||
dsp_host_interrupt = host_interrupt;
|
||||
memset(&dsp_core, 0, sizeof(dsp_core_t));
|
||||
|
||||
/* Initialize Y:rom[0x0100-0x01ff] with a sin table */
|
||||
for (i=0;i<256;i++) {
|
||||
float src = (((float) i)*M_PI)/128.0;
|
||||
Sint32 dest = (Sint32) (sin(src) * 8388608.0); /* 1<<23 */
|
||||
if (dest>8388607) {
|
||||
dest = 8388607;
|
||||
} else if (dest<-8388608) {
|
||||
dest = -8388608;
|
||||
}
|
||||
dsp_core.rom[DSP_SPACE_Y][0x100+i]=dest & 0x00ffffff;
|
||||
}
|
||||
|
||||
/* Initialize X:rom[0x0100-0x017f] with a mu-law table */
|
||||
{
|
||||
const Uint16 mulaw_base[8]={
|
||||
0x7d7c, 0x3e7c, 0x1efc, 0x0f3c, 0x075c, 0x036c, 0x0174, 0x0078
|
||||
};
|
||||
|
||||
Uint32 position = 0x0100;
|
||||
Uint32 offset = 0x040000;
|
||||
|
||||
for(i=0;i<8;i++) {
|
||||
int j;
|
||||
Uint32 value = mulaw_base[i]<<8;
|
||||
|
||||
for (j=0;j<16;j++) {
|
||||
dsp_core.rom[DSP_SPACE_X][position++]=value;
|
||||
value -= offset;
|
||||
}
|
||||
|
||||
offset >>= 1;
|
||||
}
|
||||
}
|
||||
|
||||
/* Initialize X:rom[0x0180-0x01ff] with a a-law table */
|
||||
{
|
||||
const Sint32 multiply_base[8]={
|
||||
0x1580, 0x0ac0, 0x5600, 0x2b00,
|
||||
0x1580, 0x0058, 0x0560, 0x02b0
|
||||
};
|
||||
const Sint32 multiply_col[4]={0x10, 0x01, 0x04, 0x02};
|
||||
const Sint32 multiply_line[4]={0x40, 0x04, 0x10, 0x08};
|
||||
const Sint32 base_values[4]={0, -1, 2, 1};
|
||||
Uint32 pos=0x0180;
|
||||
|
||||
for (i=0;i<8;i++) {
|
||||
Sint32 alawbase, j;
|
||||
|
||||
alawbase = multiply_base[i]<<8;
|
||||
for (j=0;j<4;j++) {
|
||||
Sint32 alawbase1, k;
|
||||
|
||||
alawbase1 = alawbase + ((base_values[j]*multiply_line[i & 3])<<12);
|
||||
|
||||
for (k=0;k<4;k++) {
|
||||
Sint32 alawbase2;
|
||||
|
||||
alawbase2 = alawbase1 + ((base_values[k]*multiply_col[i & 3])<<12);
|
||||
|
||||
dsp_core.rom[DSP_SPACE_X][pos++]=alawbase2;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Shutdown DSP emulation */
|
||||
void dsp_core_shutdown(void)
|
||||
{
|
||||
dsp_core.running = 0;
|
||||
LOG_TRACE(TRACE_DSP_STATE, "Dsp: core shutdown\n");
|
||||
}
|
||||
|
||||
/* Reset */
|
||||
void dsp_core_reset(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
LOG_TRACE(TRACE_DSP_STATE, "Dsp: core reset\n");
|
||||
dsp_core_shutdown();
|
||||
|
||||
/* Memory */
|
||||
memset((void*)dsp_core.periph, 0, sizeof(dsp_core.periph));
|
||||
memset(dsp_core.stack, 0, sizeof(dsp_core.stack));
|
||||
memset(dsp_core.registers, 0, sizeof(dsp_core.registers));
|
||||
dsp_core.dsp_host_rtx = 0;
|
||||
dsp_core.dsp_host_htx = 0;
|
||||
|
||||
dsp_core.bootstrap_pos = 0;
|
||||
|
||||
/* Registers */
|
||||
dsp_core.pc = 0x0000;
|
||||
dsp_core.registers[DSP_REG_OMR]=0x02;
|
||||
for (i=0;i<8;i++) {
|
||||
dsp_core.registers[DSP_REG_M0+i]=0x00ffff;
|
||||
}
|
||||
|
||||
/* Interruptions */
|
||||
memset((void*)dsp_core.interrupt_isPending, 0, sizeof(dsp_core.interrupt_isPending));
|
||||
dsp_core.interrupt_state = DSP_INTERRUPT_NONE;
|
||||
dsp_core.interrupt_instr_fetch = -1;
|
||||
dsp_core.interrupt_save_pc = -1;
|
||||
dsp_core.interrupt_counter = 0;
|
||||
dsp_core.interrupt_pipeline_count = 0;
|
||||
for (i=0;i<5;i++) {
|
||||
dsp_core.interrupt_ipl[i] = 3;
|
||||
}
|
||||
for (i=5;i<12;i++) {
|
||||
dsp_core.interrupt_ipl[i] = -1;
|
||||
}
|
||||
|
||||
/* host port init, dsp side */
|
||||
dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR]=(1<<DSP_HOST_HSR_HTDE);
|
||||
|
||||
/* host port init, cpu side */
|
||||
dsp_core.hostport[CPU_HOST_ICR] = 0x0;
|
||||
dsp_core.hostport[CPU_HOST_CVR] = 0x12;
|
||||
dsp_core.hostport[CPU_HOST_ISR] = (1<<CPU_HOST_ISR_TRDY)|(1<<CPU_HOST_ISR_TXDE);
|
||||
dsp_core.hostport[CPU_HOST_IVR] = 0x0f;
|
||||
dsp_core.hostport[CPU_HOST_RX0] = 0x0;
|
||||
|
||||
/* SSI registers */
|
||||
dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR]=1<<DSP_SSI_SR_TDE;
|
||||
dsp_core.ssi.waitFrameTX = 1;
|
||||
dsp_core.ssi.waitFrameRX = 1;
|
||||
dsp_core.ssi.TX = 0;
|
||||
dsp_core.ssi.RX = 0;
|
||||
dsp_core.ssi.dspPlay_handshakeMode_frame = 0;
|
||||
dsp_core_ssi_configure(DSP_SSI_CRA, 0);
|
||||
dsp_core_ssi_configure(DSP_SSI_CRB, 0);
|
||||
|
||||
/* Other hardware registers */
|
||||
dsp_core.periph[DSP_SPACE_X][DSP_IPR]=0;
|
||||
dsp_core.periph[DSP_SPACE_X][DSP_BCR]=0xffff;
|
||||
|
||||
/* Misc */
|
||||
dsp_core.loop_rep = 0;
|
||||
|
||||
LOG_TRACE(TRACE_DSP_STATE, "Dsp: reset done\n");
|
||||
dsp56k_init_cpu();
|
||||
}
|
||||
|
||||
/*
|
||||
SSI INTERFACE processing
|
||||
*/
|
||||
|
||||
/* Set PortC data register : send a frame order to the DMA in handshake mode */
|
||||
void dsp_core_setPortCDataRegister(Uint32 value)
|
||||
{
|
||||
/* if DSP Record is in handshake mode with DMA Play */
|
||||
if ((dsp_core.periph[DSP_SPACE_X][DSP_PCDDR] & 0x10) == 0x10) {
|
||||
if ((value & 0x10) == 0x10) {
|
||||
dsp_core.ssi.waitFrameRX = 0;
|
||||
DSP_SsiTransmit_SC1();
|
||||
LOG_TRACE(TRACE_DSP_HOST_SSI, "Dsp record in handshake mode: SSI send SC1 to crossbar\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* if DSP Play is in handshake mode with DMA Record, high or low frame sync */
|
||||
/* to allow / disable transfer of the data */
|
||||
if ((dsp_core.periph[DSP_SPACE_X][DSP_PCDDR] & 0x20) == 0x20) {
|
||||
if ((value & 0x20) == 0x20) {
|
||||
dsp_core.ssi.dspPlay_handshakeMode_frame = 1;
|
||||
dsp_core.ssi.waitFrameTX = 0;
|
||||
LOG_TRACE(TRACE_DSP_HOST_SSI, "Dsp play in handshake mode: frame = 1\n");
|
||||
}
|
||||
else {
|
||||
dsp_core.ssi.dspPlay_handshakeMode_frame = 0;
|
||||
DSP_SsiTransmit_SC2(0);
|
||||
LOG_TRACE(TRACE_DSP_HOST_SSI, "Dsp play in handshake mode: SSI send SC2 to crossbar, frame sync = 0\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* SSI set TX register */
|
||||
void dsp_core_ssi_writeTX(Uint32 value)
|
||||
{
|
||||
/* Clear SSI TDE bit */
|
||||
dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] &= 0xff-(1<<DSP_SSI_SR_TDE);
|
||||
dsp_core.ssi.TX = value;
|
||||
LOG_TRACE(TRACE_DSP_HOST_SSI, "Dsp set TX register: 0x%06x\n", value);
|
||||
|
||||
/* if DSP Play is in handshake mode with DMA Record, send frame sync */
|
||||
/* to allow transfer of the data */
|
||||
if (dsp_core.ssi.dspPlay_handshakeMode_frame) {
|
||||
DSP_SsiTransmit_SC2(1);
|
||||
LOG_TRACE(TRACE_DSP_HOST_SSI, "Dsp play in handshake mode: SSI send SC2 to crossbar, frame sync = 1\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* SSI set TDE register (dummy write) */
|
||||
void dsp_core_ssi_writeTSR(void)
|
||||
{
|
||||
/* Dummy write : Just clear SSI TDE bit */
|
||||
dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] &= 0xff-(1<<DSP_SSI_SR_TDE);
|
||||
}
|
||||
|
||||
/* SSI get RX register */
|
||||
Uint32 dsp_core_ssi_readRX(void)
|
||||
{
|
||||
/* Clear SSI RDF bit */
|
||||
dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] &= 0xff-(1<<DSP_SSI_SR_RDF);
|
||||
LOG_TRACE(TRACE_DSP_HOST_SSI, "Dsp read RX register: 0x%06x\n", dsp_core.ssi.RX);
|
||||
return dsp_core.ssi.RX;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* SSI receive serial clock.
|
||||
*
|
||||
*/
|
||||
void dsp_core_ssi_Receive_SC0(void)
|
||||
{
|
||||
Uint32 value, i, temp=0;
|
||||
|
||||
/* Receive data from crossbar to SSI */
|
||||
value = dsp_core.ssi.received_value;
|
||||
|
||||
/* adjust value to receive size word */
|
||||
value <<= (24 - dsp_core.ssi.cra_word_length);
|
||||
value &= 0xffffff;
|
||||
|
||||
/* if bit SHFD in CRB is set, swap received data */
|
||||
if (dsp_core.ssi.crb_shifter) {
|
||||
temp=0;
|
||||
for (i=0; i<dsp_core.ssi.cra_word_length; i++) {
|
||||
temp += value & 1;
|
||||
temp <<= 1;
|
||||
value >>= 1;
|
||||
}
|
||||
value = temp;
|
||||
}
|
||||
|
||||
LOG_TRACE(TRACE_DSP_HOST_SSI, "Dsp SSI received value from crossbar: 0x%06x\n", value);
|
||||
|
||||
if (dsp_core.ssi.crb_re && dsp_core.ssi.waitFrameRX == 0) {
|
||||
/* Send value to DSP receive */
|
||||
dsp_core.ssi.RX = value;
|
||||
|
||||
/* generate interrupt ? */
|
||||
if (dsp_core.periph[DSP_SPACE_X][DSP_SSI_CRB] & (1<<DSP_SSI_CRB_RIE)) {
|
||||
if (dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] & (1<<DSP_SSI_SR_RDF)) {
|
||||
dsp_add_interrupt(DSP_INTER_SSI_RCV_DATA);
|
||||
} else {
|
||||
dsp_add_interrupt(DSP_INTER_SSI_RCV_DATA);
|
||||
}
|
||||
}
|
||||
}else{
|
||||
dsp_core.ssi.RX = 0;
|
||||
}
|
||||
|
||||
/* set RDF */
|
||||
dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] |= 1<<DSP_SSI_SR_RDF;
|
||||
}
|
||||
|
||||
/**
|
||||
* SSI receive SC1 bit : frame sync for receiver
|
||||
* value = 1 : beginning of a new frame
|
||||
* value = 0 : not beginning of a new frame
|
||||
*/
|
||||
void dsp_core_ssi_Receive_SC1(Uint32 value)
|
||||
{
|
||||
/* SSI runs in network mode ? */
|
||||
if (dsp_core.ssi.crb_mode) {
|
||||
if (value) {
|
||||
/* Beginning of a new frame */
|
||||
dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] |= (1<<DSP_SSI_SR_RFS);
|
||||
dsp_core.ssi.waitFrameRX = 0;
|
||||
}else{
|
||||
dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] &= 0xff-(1<<DSP_SSI_SR_RFS);
|
||||
}
|
||||
}else{
|
||||
/* SSI runs in normal mode */
|
||||
dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] |= (1<<DSP_SSI_SR_RFS);
|
||||
}
|
||||
|
||||
LOG_TRACE(TRACE_DSP_HOST_SSI, "Dsp SSI receive frame sync: 0x%01x\n", value);
|
||||
}
|
||||
|
||||
/**
|
||||
* SSI receive SC2 bit : frame sync for transmitter
|
||||
* value = 1 : beginning of a new frame
|
||||
* value = 0 : not beginning of a new frame
|
||||
*/
|
||||
void dsp_core_ssi_Receive_SC2(Uint32 value)
|
||||
{
|
||||
/* SSI runs in network mode ? */
|
||||
if (dsp_core.ssi.crb_mode) {
|
||||
if (value) {
|
||||
/* Beginning of a new frame */
|
||||
dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] |= (1<<DSP_SSI_SR_TFS);
|
||||
dsp_core.ssi.waitFrameTX = 0;
|
||||
}else{
|
||||
dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] &= 0xff-(1<<DSP_SSI_SR_TFS);
|
||||
}
|
||||
}else{
|
||||
/* SSI runs in normal mode */
|
||||
dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] |= (1<<DSP_SSI_SR_TFS);
|
||||
}
|
||||
|
||||
LOG_TRACE(TRACE_DSP_HOST_SSI, "Dsp SSI transmit frame sync: 0x%01x\n", value);
|
||||
}
|
||||
|
||||
/**
|
||||
* SSI transmit serial clock.
|
||||
*
|
||||
*/
|
||||
void dsp_core_ssi_Receive_SCK(void)
|
||||
{
|
||||
Uint32 value, i, temp=0;
|
||||
|
||||
value = dsp_core.ssi.TX;
|
||||
|
||||
/* Transfer data from SSI to crossbar*/
|
||||
|
||||
/* adjust value to transnmit size word */
|
||||
value >>= (24 - dsp_core.ssi.cra_word_length);
|
||||
value &= dsp_core.ssi.cra_word_mask;
|
||||
|
||||
/* if bit SHFD in CRB is set, swap data to transmit */
|
||||
if (dsp_core.ssi.crb_shifter) {
|
||||
for (i=0; i<dsp_core.ssi.cra_word_length; i++) {
|
||||
temp += value & 1;
|
||||
temp <<= 1;
|
||||
value >>= 1;
|
||||
}
|
||||
value = temp;
|
||||
}
|
||||
|
||||
LOG_TRACE(TRACE_DSP_HOST_SSI, "Dsp SSI transmit value to crossbar: 0x%06x\n", value);
|
||||
|
||||
/* Transmit the data */
|
||||
if (dsp_core.ssi.crb_te && dsp_core.ssi.waitFrameTX == 0) {
|
||||
/* Send value to crossbar */
|
||||
dsp_core.ssi.transmit_value = value;
|
||||
|
||||
/* generate interrupt ? */
|
||||
if (dsp_core.periph[DSP_SPACE_X][DSP_SSI_CRB] & (1<<DSP_SSI_CRB_TIE)) {
|
||||
if (dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] & (1<<DSP_SSI_SR_TDE)) {
|
||||
dsp_add_interrupt(DSP_INTER_SSI_TRX_DATA);
|
||||
} else {
|
||||
dsp_add_interrupt(DSP_INTER_SSI_TRX_DATA);
|
||||
}
|
||||
}
|
||||
}else{
|
||||
dsp_core.ssi.transmit_value = 0;
|
||||
}
|
||||
|
||||
/* set TDE */
|
||||
dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] |= (1<<DSP_SSI_SR_TDE);
|
||||
}
|
||||
|
||||
|
||||
/* SSI initialisations and state management */
|
||||
void dsp_core_ssi_configure(Uint32 address, Uint32 value)
|
||||
{
|
||||
Uint32 crb_te, crb_re;
|
||||
|
||||
switch (address) {
|
||||
case DSP_SSI_CRA:
|
||||
dsp_core.periph[DSP_SPACE_X][DSP_SSI_CRA] = value;
|
||||
/* get word size for transfers */
|
||||
switch ((value>>DSP_SSI_CRA_WL0) & 3) {
|
||||
case 0:
|
||||
dsp_core.ssi.cra_word_length = 8;
|
||||
dsp_core.ssi.cra_word_mask = 0xff;
|
||||
break;
|
||||
case 1:
|
||||
dsp_core.ssi.cra_word_length = 12;
|
||||
dsp_core.ssi.cra_word_mask = 0xfff;
|
||||
break;
|
||||
case 2:
|
||||
dsp_core.ssi.cra_word_length = 16;
|
||||
dsp_core.ssi.cra_word_mask = 0xffff;
|
||||
break;
|
||||
case 3:
|
||||
dsp_core.ssi.cra_word_length = 24;
|
||||
dsp_core.ssi.cra_word_mask = 0xffffff;
|
||||
break;
|
||||
}
|
||||
|
||||
LOG_TRACE(TRACE_DSP_HOST_SSI, "Dsp SSI CRA write: 0x%06x\n", value);
|
||||
|
||||
/* Get the Frame rate divider ( 2 < value <32) */
|
||||
dsp_core.ssi.cra_frame_rate_divider = ((value >> DSP_SSI_CRA_DC0) & 0x1f)+1;
|
||||
break;
|
||||
case DSP_SSI_CRB:
|
||||
crb_te = dsp_core.periph[DSP_SPACE_X][DSP_SSI_CRB] & (1<<DSP_SSI_CRB_TE);
|
||||
crb_re = dsp_core.periph[DSP_SPACE_X][DSP_SSI_CRB] & (1<<DSP_SSI_CRB_RE);
|
||||
dsp_core.periph[DSP_SPACE_X][DSP_SSI_CRB] = value;
|
||||
|
||||
dsp_core.ssi.crb_src_clock = (value>>DSP_SSI_CRB_SCKD) & 1;
|
||||
dsp_core.ssi.crb_shifter = (value>>DSP_SSI_CRB_SHFD) & 1;
|
||||
dsp_core.ssi.crb_synchro = (value>>DSP_SSI_CRB_SYN) & 1;
|
||||
dsp_core.ssi.crb_mode = (value>>DSP_SSI_CRB_MOD) & 1;
|
||||
dsp_core.ssi.crb_te = (value>>DSP_SSI_CRB_TE) & 1;
|
||||
dsp_core.ssi.crb_re = (value>>DSP_SSI_CRB_RE) & 1;
|
||||
dsp_core.ssi.crb_tie = (value>>DSP_SSI_CRB_TIE) & 1;
|
||||
dsp_core.ssi.crb_rie = (value>>DSP_SSI_CRB_RIE) & 1;
|
||||
|
||||
if (crb_te == 0 && dsp_core.ssi.crb_te) {
|
||||
dsp_core.ssi.waitFrameTX = 1;
|
||||
}
|
||||
if (crb_re == 0 && dsp_core.ssi.crb_re) {
|
||||
dsp_core.ssi.waitFrameRX = 1;
|
||||
}
|
||||
|
||||
LOG_TRACE(TRACE_DSP_HOST_SSI, "Dsp SSI CRB write: 0x%06x\n", value);
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
HOST INTERFACE processing
|
||||
*/
|
||||
|
||||
static void dsp_core_hostport_update_trdy(void)
|
||||
{
|
||||
int trdy;
|
||||
|
||||
/* Clear/set TRDY bit */
|
||||
dsp_core.hostport[CPU_HOST_ISR] &= 0xff-(1<<CPU_HOST_ISR_TRDY);
|
||||
trdy = (dsp_core.hostport[CPU_HOST_ISR]>>CPU_HOST_ISR_TXDE)
|
||||
& ~(dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR]>>DSP_HOST_HSR_HRDF);
|
||||
dsp_core.hostport[CPU_HOST_ISR] |= (trdy & 1)<< CPU_HOST_ISR_TRDY;
|
||||
}
|
||||
|
||||
static void dsp_core_hostport_update_hreq(void)
|
||||
{
|
||||
int hreq;
|
||||
|
||||
hreq = (dsp_core.hostport[CPU_HOST_ICR] & dsp_core.hostport[CPU_HOST_ISR]) & 0x3;
|
||||
|
||||
/* Trigger host interrupt? */
|
||||
if (hreq && (dsp_core.hostport[CPU_HOST_ISR] & (1<<CPU_HOST_ISR_HREQ)) == 0) {
|
||||
dsp_host_interrupt();
|
||||
}
|
||||
|
||||
/* Set HREQ bit in hostport */
|
||||
dsp_core.hostport[CPU_HOST_ISR] &= 0x7f;
|
||||
dsp_core.hostport[CPU_HOST_ISR] |= (hreq?1:0) << CPU_HOST_ISR_HREQ;
|
||||
}
|
||||
|
||||
/* Host port transfer ? (dsp->host) */
|
||||
static void dsp_core_dsp2host(void)
|
||||
{
|
||||
/* RXDF = 1 ==> host hasn't read the last value yet */
|
||||
if (dsp_core.hostport[CPU_HOST_ISR] & (1<<CPU_HOST_ISR_RXDF)) {
|
||||
return;
|
||||
}
|
||||
|
||||
/* HTDE = 1 ==> nothing to tranfert from DSP port */
|
||||
if (dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] & (1<<DSP_HOST_HSR_HTDE)) {
|
||||
return;
|
||||
}
|
||||
|
||||
dsp_core.hostport[CPU_HOST_RXL] = dsp_core.dsp_host_htx;
|
||||
dsp_core.hostport[CPU_HOST_RXM] = dsp_core.dsp_host_htx>>8;
|
||||
dsp_core.hostport[CPU_HOST_RXH] = dsp_core.dsp_host_htx>>16;
|
||||
|
||||
/* Set HTDE bit to say that DSP can write */
|
||||
dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] |= 1<<DSP_HOST_HSR_HTDE;
|
||||
|
||||
/* Is there an interrupt to send ? */
|
||||
if (dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR] & (1<<DSP_HOST_HCR_HTIE)) {
|
||||
dsp_add_interrupt(DSP_INTER_HOST_TRX_DATA);
|
||||
}
|
||||
|
||||
/* Set RXDF bit to say that host can read */
|
||||
dsp_core.hostport[CPU_HOST_ISR] |= 1<<CPU_HOST_ISR_RXDF;
|
||||
dsp_core_hostport_update_hreq();
|
||||
|
||||
LOG_TRACE(TRACE_DSP_HOST_INTERFACE, "Dsp: (DSP->Host): Transfer 0x%06x, Dsp HTDE=1, Host RXDF=1\n", dsp_core.dsp_host_htx);
|
||||
}
|
||||
|
||||
/* Host port transfer ? (host->dsp) */
|
||||
static void dsp_core_host2dsp(void)
|
||||
{
|
||||
/* TXDE = 1 ==> nothing to tranfert from host port */
|
||||
if (dsp_core.hostport[CPU_HOST_ISR] & (1<<CPU_HOST_ISR_TXDE)) {
|
||||
return;
|
||||
}
|
||||
|
||||
/* HRDF = 1 ==> DSP hasn't read the last value yet */
|
||||
if (dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] & (1<<DSP_HOST_HSR_HRDF)) {
|
||||
return;
|
||||
}
|
||||
|
||||
dsp_core.dsp_host_rtx = dsp_core.hostport[CPU_HOST_TXL];
|
||||
dsp_core.dsp_host_rtx |= dsp_core.hostport[CPU_HOST_TXM]<<8;
|
||||
dsp_core.dsp_host_rtx |= dsp_core.hostport[CPU_HOST_TXH]<<16;
|
||||
|
||||
/* Set HRDF bit to say that DSP can read */
|
||||
dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] |= 1<<DSP_HOST_HSR_HRDF;
|
||||
|
||||
/* Is there an interrupt to send ? */
|
||||
if (dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR] & (1<<DSP_HOST_HCR_HRIE)) {
|
||||
dsp_add_interrupt(DSP_INTER_HOST_RCV_DATA);
|
||||
}
|
||||
|
||||
/* Set TXDE bit to say that host can write */
|
||||
dsp_core.hostport[CPU_HOST_ISR] |= 1<<CPU_HOST_ISR_TXDE;
|
||||
dsp_core_hostport_update_hreq();
|
||||
|
||||
LOG_TRACE(TRACE_DSP_HOST_INTERFACE, "Dsp: (Host->DSP): Transfer 0x%06x, Dsp HRDF=1, Host TXDE=1\n", dsp_core.dsp_host_rtx);
|
||||
|
||||
dsp_core_hostport_update_trdy();
|
||||
}
|
||||
|
||||
void dsp_core_hostport_dspread(void)
|
||||
{
|
||||
/* Clear HRDF bit to say that DSP has read */
|
||||
dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] &= 0xff-(1<<DSP_HOST_HSR_HRDF);
|
||||
|
||||
LOG_TRACE(TRACE_DSP_HOST_INTERFACE, "Dsp: (Host->DSP): Dsp HRDF cleared\n");
|
||||
|
||||
dsp_core_hostport_update_trdy();
|
||||
dsp_core_host2dsp();
|
||||
}
|
||||
|
||||
void dsp_core_hostport_dspwrite(void)
|
||||
{
|
||||
/* Clear HTDE bit to say that DSP has written */
|
||||
dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] &= 0xff-(1<<DSP_HOST_HSR_HTDE);
|
||||
|
||||
LOG_TRACE(TRACE_DSP_HOST_INTERFACE, "Dsp: (DSP->Host): Dsp HTDE cleared\n");
|
||||
|
||||
dsp_core_dsp2host();
|
||||
}
|
||||
|
||||
/* Read/writes on host port */
|
||||
Uint8 dsp_core_read_host(int addr)
|
||||
{
|
||||
Uint8 value;
|
||||
|
||||
value = dsp_core.hostport[addr];
|
||||
if (addr == CPU_HOST_TRXL) {
|
||||
/* Clear RXDF bit to say that CPU has read */
|
||||
dsp_core.hostport[CPU_HOST_ISR] &= 0xff-(1<<CPU_HOST_ISR_RXDF);
|
||||
dsp_core_dsp2host();
|
||||
dsp_core_hostport_update_hreq();
|
||||
|
||||
LOG_TRACE(TRACE_DSP_HOST_INTERFACE, "Dsp: (DSP->Host): Host RXDF=0\n");
|
||||
}
|
||||
return value;
|
||||
}
|
||||
|
||||
void dsp_core_write_host(int addr, Uint8 value)
|
||||
{
|
||||
switch(addr) {
|
||||
case CPU_HOST_ICR:
|
||||
dsp_core.hostport[CPU_HOST_ICR]=value & 0xfb;
|
||||
/* Set HF1 and HF0 accordingly on the host side */
|
||||
dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] &=
|
||||
0xff-((1<<DSP_HOST_HSR_HF1)|(1<<DSP_HOST_HSR_HF0));
|
||||
dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] |=
|
||||
dsp_core.hostport[CPU_HOST_ICR] & ((1<<DSP_HOST_HSR_HF1)|(1<<DSP_HOST_HSR_HF0));
|
||||
dsp_core_hostport_update_hreq();
|
||||
break;
|
||||
case CPU_HOST_CVR:
|
||||
dsp_core.hostport[CPU_HOST_CVR]=value & 0x9f;
|
||||
/* if bit 7=1, host command . HSR(bit HCP) is set*/
|
||||
if (value & (1<<7)) {
|
||||
dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] |= (1<<DSP_HOST_HSR_HCP);
|
||||
/* Is there an interrupt to send ? */
|
||||
if (dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR] & (1<<DSP_HOST_HCR_HCIE)) {
|
||||
dsp_add_interrupt(DSP_INTER_HOST_COMMAND);
|
||||
}
|
||||
}
|
||||
else{
|
||||
dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] &= 0xff - (1<<DSP_HOST_HSR_HCP);
|
||||
}
|
||||
|
||||
LOG_TRACE(TRACE_DSP_HOST_COMMAND, "Dsp: (Host->DSP): Host command = %06x\n", value & 0x9f);
|
||||
|
||||
break;
|
||||
case CPU_HOST_ISR:
|
||||
case CPU_HOST_TRX0:
|
||||
/* Read only */
|
||||
break;
|
||||
case CPU_HOST_IVR:
|
||||
dsp_core.hostport[CPU_HOST_IVR]=value;
|
||||
break;
|
||||
case CPU_HOST_TRXH:
|
||||
dsp_core.hostport[CPU_HOST_TXH]=value;
|
||||
break;
|
||||
case CPU_HOST_TRXM:
|
||||
dsp_core.hostport[CPU_HOST_TXM]=value;
|
||||
break;
|
||||
case CPU_HOST_TRXL:
|
||||
dsp_core.hostport[CPU_HOST_TXL]=value;
|
||||
|
||||
if (!dsp_core.running) {
|
||||
dsp_core.ramint[DSP_SPACE_P][dsp_core.bootstrap_pos] =
|
||||
(dsp_core.hostport[CPU_HOST_TXH]<<16) |
|
||||
(dsp_core.hostport[CPU_HOST_TXM]<<8) |
|
||||
dsp_core.hostport[CPU_HOST_TXL];
|
||||
|
||||
LOG_TRACE(TRACE_DSP_STATE, "Dsp: bootstrap p:0x%04x = 0x%06x\n",
|
||||
dsp_core.bootstrap_pos,
|
||||
dsp_core.ramint[DSP_SPACE_P][dsp_core.bootstrap_pos]);
|
||||
|
||||
if (++dsp_core.bootstrap_pos == 0x200) {
|
||||
LOG_TRACE(TRACE_DSP_STATE, "Dsp: wait bootstrap done\n");
|
||||
dsp_core.running = 1;
|
||||
}
|
||||
} else {
|
||||
|
||||
/* If TRDY is set, the tranfert is direct to DSP (Burst mode) */
|
||||
if (dsp_core.hostport[CPU_HOST_ISR] & (1<<CPU_HOST_ISR_TRDY)){
|
||||
dsp_core.dsp_host_rtx = dsp_core.hostport[CPU_HOST_TXL];
|
||||
dsp_core.dsp_host_rtx |= dsp_core.hostport[CPU_HOST_TXM]<<8;
|
||||
dsp_core.dsp_host_rtx |= dsp_core.hostport[CPU_HOST_TXH]<<16;
|
||||
|
||||
LOG_TRACE(TRACE_DSP_HOST_INTERFACE, "Dsp: (Host->DSP): Direct Transfer 0x%06x\n", dsp_core.dsp_host_rtx);
|
||||
|
||||
/* Set HRDF bit to say that DSP can read */
|
||||
dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] |= 1<<DSP_HOST_HSR_HRDF;
|
||||
|
||||
/* Is there an interrupt to send ? */
|
||||
if (dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR] & (1<<DSP_HOST_HCR_HRIE)) {
|
||||
dsp_add_interrupt(DSP_INTER_HOST_RCV_DATA);
|
||||
}
|
||||
|
||||
LOG_TRACE(TRACE_DSP_HOST_INTERFACE, "Dsp: (Host->DSP): Dsp HRDF set\n");
|
||||
}
|
||||
else{
|
||||
/* Clear TXDE to say that CPU has written */
|
||||
dsp_core.hostport[CPU_HOST_ISR] &= 0xff-(1<<CPU_HOST_ISR_TXDE);
|
||||
dsp_core_hostport_update_hreq();
|
||||
|
||||
LOG_TRACE(TRACE_DSP_HOST_INTERFACE, "Dsp: (Host->DSP): Host TXDE cleared\n");
|
||||
}
|
||||
dsp_core_hostport_update_trdy();
|
||||
dsp_core_host2dsp();
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
vim:ts=4:sw=4:
|
||||
*/
|
||||
|
|
@ -0,0 +1,275 @@
|
|||
/*
|
||||
DSP M56001 emulation
|
||||
Core of DSP emulation
|
||||
|
||||
(C) 2003-2008 ARAnyM developer team
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef DSP_CORE_H
|
||||
#define DSP_CORE_H
|
||||
|
||||
#include <SDL.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define DSP_RAMSIZE 32768
|
||||
|
||||
/* Host port, CPU side */
|
||||
#define CPU_HOST_ICR 0x00
|
||||
#define CPU_HOST_CVR 0x01
|
||||
#define CPU_HOST_ISR 0x02
|
||||
#define CPU_HOST_IVR 0x03
|
||||
#define CPU_HOST_TRX0 0x04
|
||||
#define CPU_HOST_TRXH 0x05
|
||||
#define CPU_HOST_TRXM 0x06
|
||||
#define CPU_HOST_TRXL 0x07
|
||||
#define CPU_HOST_RX0 0x04
|
||||
#define CPU_HOST_RXH 0x05
|
||||
#define CPU_HOST_RXM 0x06
|
||||
#define CPU_HOST_RXL 0x07
|
||||
#define CPU_HOST_TXH 0x09
|
||||
#define CPU_HOST_TXM 0x0a
|
||||
#define CPU_HOST_TXL 0x0b
|
||||
|
||||
#define CPU_HOST_ICR_RREQ 0x00
|
||||
#define CPU_HOST_ICR_TREQ 0x01
|
||||
#define CPU_HOST_ICR_HF0 0x03
|
||||
#define CPU_HOST_ICR_HF1 0x04
|
||||
#define CPU_HOST_ICR_HM0 0x05
|
||||
#define CPU_HOST_ICR_HM1 0x06
|
||||
#define CPU_HOST_ICR_INIT 0x07
|
||||
|
||||
#define CPU_HOST_CVR_HC 0x07
|
||||
|
||||
#define CPU_HOST_ISR_RXDF 0x00
|
||||
#define CPU_HOST_ISR_TXDE 0x01
|
||||
#define CPU_HOST_ISR_TRDY 0x02
|
||||
#define CPU_HOST_ISR_HF2 0x03
|
||||
#define CPU_HOST_ISR_HF3 0x04
|
||||
#define CPU_HOST_ISR_DMA 0x06
|
||||
#define CPU_HOST_ISR_HREQ 0x07
|
||||
|
||||
/* Host port, DSP side, DSP addresses are 0xffc0+value */
|
||||
#define DSP_PBC 0x20 /* Port B control register */
|
||||
#define DSP_PCC 0x21 /* Port C control register */
|
||||
#define DSP_PBDDR 0x22 /* Port B data direction register */
|
||||
#define DSP_PCDDR 0x23 /* Port C data direction register */
|
||||
#define DSP_PBD 0x24 /* Port B data register */
|
||||
#define DSP_PCD 0x25 /* Port C data register */
|
||||
#define DSP_HOST_HCR 0x28 /* Host control register */
|
||||
#define DSP_HOST_HSR 0x29 /* Host status register */
|
||||
#define DSP_HOST_HRX 0x2b /* Host receive register */
|
||||
#define DSP_HOST_HTX 0x2b /* Host transmit register */
|
||||
#define DSP_SSI_CRA 0x2c /* Ssi control register A */
|
||||
#define DSP_SSI_CRB 0x2d /* Ssi control register B */
|
||||
#define DSP_SSI_SR 0x2e /* Ssi status register */
|
||||
#define DSP_SSI_TSR 0x2e /* Ssi time slot register */
|
||||
#define DSP_SSI_RX 0x2f /* Ssi receive register */
|
||||
#define DSP_SSI_TX 0x2f /* Ssi transmit register */
|
||||
#define DSP_BCR 0x3e /* Port A bus control register */
|
||||
#define DSP_IPR 0x3f /* Interrupt priority register */
|
||||
|
||||
#define DSP_HOST_HCR_HRIE 0x00
|
||||
#define DSP_HOST_HCR_HTIE 0x01
|
||||
#define DSP_HOST_HCR_HCIE 0x02
|
||||
#define DSP_HOST_HCR_HF2 0x03
|
||||
#define DSP_HOST_HCR_HF3 0x04
|
||||
|
||||
#define DSP_HOST_HSR_HRDF 0x00
|
||||
#define DSP_HOST_HSR_HTDE 0x01
|
||||
#define DSP_HOST_HSR_HCP 0x02
|
||||
#define DSP_HOST_HSR_HF0 0x03
|
||||
#define DSP_HOST_HSR_HF1 0x04
|
||||
#define DSP_HOST_HSR_DMA 0x07
|
||||
|
||||
#define DSP_SSI_CRA_DC0 0x8
|
||||
#define DSP_SSI_CRA_DC1 0x9
|
||||
#define DSP_SSI_CRA_DC2 0xa
|
||||
#define DSP_SSI_CRA_DC3 0xb
|
||||
#define DSP_SSI_CRA_DC4 0xc
|
||||
#define DSP_SSI_CRA_WL0 0xd
|
||||
#define DSP_SSI_CRA_WL1 0xe
|
||||
|
||||
#define DSP_SSI_CRB_OF0 0x0
|
||||
#define DSP_SSI_CRB_OF1 0x1
|
||||
#define DSP_SSI_CRB_SCD0 0x2
|
||||
#define DSP_SSI_CRB_SCD1 0x3
|
||||
#define DSP_SSI_CRB_SCD2 0x4
|
||||
#define DSP_SSI_CRB_SCKD 0x5
|
||||
#define DSP_SSI_CRB_SHFD 0x6
|
||||
#define DSP_SSI_CRB_FSL0 0x7
|
||||
#define DSP_SSI_CRB_FSL1 0x8
|
||||
#define DSP_SSI_CRB_SYN 0x9
|
||||
#define DSP_SSI_CRB_GCK 0xa
|
||||
#define DSP_SSI_CRB_MOD 0xb
|
||||
#define DSP_SSI_CRB_TE 0xc
|
||||
#define DSP_SSI_CRB_RE 0xd
|
||||
#define DSP_SSI_CRB_TIE 0xe
|
||||
#define DSP_SSI_CRB_RIE 0xf
|
||||
|
||||
#define DSP_SSI_SR_IF0 0x0
|
||||
#define DSP_SSI_SR_IF1 0x1
|
||||
#define DSP_SSI_SR_TFS 0x2
|
||||
#define DSP_SSI_SR_RFS 0x3
|
||||
#define DSP_SSI_SR_TUE 0x4
|
||||
#define DSP_SSI_SR_ROE 0x5
|
||||
#define DSP_SSI_SR_TDE 0x6
|
||||
#define DSP_SSI_SR_RDF 0x7
|
||||
|
||||
#define DSP_INTERRUPT_NONE 0x0
|
||||
#define DSP_INTERRUPT_DISABLED 0x1
|
||||
#define DSP_INTERRUPT_LONG 0x2
|
||||
|
||||
#define DSP_INTER_RESET 0x0
|
||||
#define DSP_INTER_ILLEGAL 0x1
|
||||
#define DSP_INTER_STACK_ERROR 0x2
|
||||
#define DSP_INTER_TRACE 0x3
|
||||
#define DSP_INTER_SWI 0x4
|
||||
#define DSP_INTER_HOST_COMMAND 0x5
|
||||
#define DSP_INTER_HOST_RCV_DATA 0x6
|
||||
#define DSP_INTER_HOST_TRX_DATA 0x7
|
||||
#define DSP_INTER_SSI_RCV_DATA_E 0x8
|
||||
#define DSP_INTER_SSI_RCV_DATA 0x9
|
||||
#define DSP_INTER_SSI_TRX_DATA_E 0xa
|
||||
#define DSP_INTER_SSI_TRX_DATA 0xb
|
||||
|
||||
|
||||
typedef struct dsp_core_ssi_s dsp_core_ssi_t;
|
||||
typedef struct dsp_core_s dsp_core_t;
|
||||
typedef struct dsp_interrupt_s dsp_interrupt_t;
|
||||
|
||||
struct dsp_core_ssi_s {
|
||||
Uint16 cra_word_length;
|
||||
Uint32 cra_word_mask;
|
||||
Uint16 cra_frame_rate_divider;
|
||||
|
||||
Uint16 crb_src_clock;
|
||||
Uint16 crb_shifter;
|
||||
Uint16 crb_synchro;
|
||||
Uint16 crb_mode;
|
||||
Uint16 crb_te;
|
||||
Uint16 crb_re;
|
||||
Uint16 crb_tie;
|
||||
Uint16 crb_rie;
|
||||
|
||||
Uint32 TX;
|
||||
Uint32 RX;
|
||||
Uint32 transmit_value; /* DSP Transmit --> SSI */
|
||||
Uint32 received_value; /* DSP Receive --> SSI */
|
||||
Uint16 waitFrameTX;
|
||||
Uint16 waitFrameRX;
|
||||
Uint32 dspPlay_handshakeMode_frame;
|
||||
};
|
||||
|
||||
struct dsp_interrupt_s {
|
||||
const Uint16 inter;
|
||||
const Uint16 vectorAddr;
|
||||
const Uint16 periph;
|
||||
const char *name;
|
||||
};
|
||||
|
||||
|
||||
struct dsp_core_s {
|
||||
|
||||
/* DSP executing instructions ? */
|
||||
volatile int running;
|
||||
|
||||
/* DSP instruction Cycle counter */
|
||||
Uint16 instr_cycle;
|
||||
|
||||
/* Registers */
|
||||
Uint16 pc;
|
||||
Uint32 registers[64];
|
||||
|
||||
/* stack[0=ssh], stack[1=ssl] */
|
||||
Uint16 stack[2][16];
|
||||
|
||||
/* External ram[] (mapped to p:) */
|
||||
Uint32 ramext[DSP_RAMSIZE];
|
||||
|
||||
/* rom[0] is x:, rom[1] is y: */
|
||||
Uint32 rom[2][512];
|
||||
|
||||
/* Internal ram[0] is x:, ram[1] is y:, ram[2] is p: */
|
||||
Uint32 ramint[3][512];
|
||||
|
||||
/* peripheral space, [x|y]:0xffc0-0xffff */
|
||||
volatile Uint32 periph[2][64];
|
||||
volatile Uint32 dsp_host_htx;
|
||||
volatile Uint32 dsp_host_rtx;
|
||||
Uint16 dsp_host_isr_HREQ;
|
||||
|
||||
|
||||
/* host port, CPU side */
|
||||
volatile Uint8 hostport[12];
|
||||
|
||||
/* SSI */
|
||||
dsp_core_ssi_t ssi;
|
||||
|
||||
/* Misc */
|
||||
Uint32 loop_rep; /* executing rep ? */
|
||||
Uint32 pc_on_rep; /* True if PC is on REP instruction */
|
||||
|
||||
/* For bootstrap routine */
|
||||
Uint16 bootstrap_pos;
|
||||
|
||||
/* Interruptions */
|
||||
Uint16 interrupt_state; /* NONE, FAST or LONG interrupt */
|
||||
Uint16 interrupt_instr_fetch; /* vector of the current interrupt */
|
||||
Uint16 interrupt_save_pc; /* save next pc value before interrupt */
|
||||
Uint16 interrupt_counter; /* count number of pending interrupts */
|
||||
Uint16 interrupt_IplToRaise; /* save the IPL level to save in the SR register */
|
||||
Uint16 interrupt_pipeline_count; /* used to prefetch correctly the 2 inter instructions */
|
||||
Sint16 interrupt_ipl[12]; /* store the current IPL for each interrupt */
|
||||
Uint16 interrupt_isPending[12]; /* store if interrupt is pending for each interrupt */
|
||||
};
|
||||
|
||||
|
||||
/* DSP */
|
||||
extern dsp_core_t dsp_core;
|
||||
|
||||
/* Emulator call these to init/stop/reset DSP emulation */
|
||||
extern void dsp_core_init(void (*host_interrupt)(void));
|
||||
extern void dsp_core_shutdown(void);
|
||||
extern void dsp_core_reset(void);
|
||||
|
||||
/* host port read/write by emulator, addr is 0-7, not 0xffa200-0xffa207 */
|
||||
extern Uint8 dsp_core_read_host(int addr);
|
||||
extern void dsp_core_write_host(int addr, Uint8 value);
|
||||
|
||||
/* dsp_cpu call these to read/write host port */
|
||||
extern void dsp_core_hostport_dspread(void);
|
||||
extern void dsp_core_hostport_dspwrite(void);
|
||||
|
||||
/* dsp_cpu call these to read/write/configure SSI port */
|
||||
extern void dsp_core_ssi_configure(Uint32 address, Uint32 value);
|
||||
extern void dsp_core_ssi_writeTX(Uint32 value);
|
||||
extern void dsp_core_ssi_writeTSR(void);
|
||||
extern Uint32 dsp_core_ssi_readRX(void);
|
||||
extern void dsp_core_ssi_Receive_SC0(void);
|
||||
extern void dsp_core_ssi_Receive_SC1(Uint32 value);
|
||||
extern void dsp_core_ssi_Receive_SC2(Uint32 value);
|
||||
extern void dsp_core_ssi_Receive_SCK(void);
|
||||
extern void dsp_core_setPortCDataRegister(Uint32 value);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DSP_CORE_H */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,125 @@
|
|||
/*
|
||||
DSP M56001 emulation
|
||||
Instructions interpreter, execution thread
|
||||
|
||||
(C) 2003-2008 ARAnyM developer team
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef DSP_CPU_H
|
||||
#define DSP_CPU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Defines */
|
||||
#define BITMASK(x) ((1<<(x))-1)
|
||||
|
||||
#define DSP_OMR_MA 0x00
|
||||
#define DSP_OMR_MB 0x01
|
||||
#define DSP_OMR_DE 0x02
|
||||
#define DSP_OMR_SD 0x06
|
||||
#define DSP_OMR_EA 0x07
|
||||
|
||||
#define DSP_SR_C 0x00
|
||||
#define DSP_SR_V 0x01
|
||||
#define DSP_SR_Z 0x02
|
||||
#define DSP_SR_N 0x03
|
||||
#define DSP_SR_U 0x04
|
||||
#define DSP_SR_E 0x05
|
||||
#define DSP_SR_L 0x06
|
||||
|
||||
#define DSP_SR_I0 0x08
|
||||
#define DSP_SR_I1 0x09
|
||||
#define DSP_SR_S0 0x0a
|
||||
#define DSP_SR_S1 0x0b
|
||||
#define DSP_SR_T 0x0d
|
||||
#define DSP_SR_LF 0x0f
|
||||
|
||||
#define DSP_SP_SE 0x04
|
||||
#define DSP_SP_UF 0x05
|
||||
|
||||
/* Registers numbers in dsp.registers[] */
|
||||
#define DSP_REG_X0 0x04
|
||||
#define DSP_REG_X1 0x05
|
||||
#define DSP_REG_Y0 0x06
|
||||
#define DSP_REG_Y1 0x07
|
||||
#define DSP_REG_A0 0x08
|
||||
#define DSP_REG_B0 0x09
|
||||
#define DSP_REG_A2 0x0a
|
||||
#define DSP_REG_B2 0x0b
|
||||
#define DSP_REG_A1 0x0c
|
||||
#define DSP_REG_B1 0x0d
|
||||
#define DSP_REG_A 0x0e
|
||||
#define DSP_REG_B 0x0f
|
||||
|
||||
#define DSP_REG_R0 0x10
|
||||
#define DSP_REG_R1 0x11
|
||||
#define DSP_REG_R2 0x12
|
||||
#define DSP_REG_R3 0x13
|
||||
#define DSP_REG_R4 0x14
|
||||
#define DSP_REG_R5 0x15
|
||||
#define DSP_REG_R6 0x16
|
||||
#define DSP_REG_R7 0x17
|
||||
|
||||
#define DSP_REG_N0 0x18
|
||||
#define DSP_REG_N1 0x19
|
||||
#define DSP_REG_N2 0x1a
|
||||
#define DSP_REG_N3 0x1b
|
||||
#define DSP_REG_N4 0x1c
|
||||
#define DSP_REG_N5 0x1d
|
||||
#define DSP_REG_N6 0x1e
|
||||
#define DSP_REG_N7 0x1f
|
||||
|
||||
#define DSP_REG_M0 0x20
|
||||
#define DSP_REG_M1 0x21
|
||||
#define DSP_REG_M2 0x22
|
||||
#define DSP_REG_M3 0x23
|
||||
#define DSP_REG_M4 0x24
|
||||
#define DSP_REG_M5 0x25
|
||||
#define DSP_REG_M6 0x26
|
||||
#define DSP_REG_M7 0x27
|
||||
|
||||
#define DSP_REG_SR 0x39
|
||||
#define DSP_REG_OMR 0x3a
|
||||
#define DSP_REG_SP 0x3b
|
||||
#define DSP_REG_SSH 0x3c
|
||||
#define DSP_REG_SSL 0x3d
|
||||
#define DSP_REG_LA 0x3e
|
||||
#define DSP_REG_LC 0x3f
|
||||
|
||||
#define DSP_REG_NULL 0x00
|
||||
#define DSP_REG_LCSAVE 0x30
|
||||
|
||||
/* Memory spaces for dsp.ram[], dsp.rom[] */
|
||||
#define DSP_SPACE_X 0x00
|
||||
#define DSP_SPACE_Y 0x01
|
||||
#define DSP_SPACE_P 0x02
|
||||
|
||||
/* Functions */
|
||||
extern void dsp56k_init_cpu(void); /* Set dsp_core to use */
|
||||
extern void dsp56k_execute_instruction(void); /* Execute 1 instruction */
|
||||
extern Uint16 dsp56k_execute_one_disasm_instruction(FILE *out, Uint16 pc); /* Execute 1 instruction in disasm mode */
|
||||
|
||||
/* Interrupt relative functions */
|
||||
void dsp_add_interrupt(Uint16 inter);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DSP_CPU_H */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,47 @@
|
|||
/*
|
||||
DSP M56001 emulation
|
||||
Disassembler
|
||||
|
||||
(C) 2003-2008 ARAnyM developer team
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef DSP_DISASM_H
|
||||
#define DSP_DISASM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
DSP_TRACE_MODE,
|
||||
DSP_DISASM_MODE
|
||||
} dsp_trace_disasm_t;
|
||||
|
||||
/* Functions */
|
||||
extern void dsp56k_disasm_init(void);
|
||||
extern Uint16 dsp56k_disasm(dsp_trace_disasm_t value);
|
||||
extern const char* dsp56k_getInstructionText(void);
|
||||
|
||||
/* Registers change */
|
||||
extern void dsp56k_disasm_reg_save(void);
|
||||
extern void dsp56k_disasm_reg_compare(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DSP_DISASM_H */
|
||||
Loading…
Reference in New Issue