mirror of https://github.com/xemu-project/xemu.git
alpha-linux-user: Handle TARGET_SSI_IEEE_RAISE_EXCEPTION properly
We weren't aggregating the exceptions, nor raising signals properly. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
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@ -7699,13 +7699,13 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
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ret = -TARGET_EOPNOTSUPP;
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ret = -TARGET_EOPNOTSUPP;
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switch (arg1) {
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switch (arg1) {
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case TARGET_SSI_IEEE_FP_CONTROL:
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case TARGET_SSI_IEEE_FP_CONTROL:
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case TARGET_SSI_IEEE_RAISE_EXCEPTION:
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{
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{
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uint64_t swcr, fpcr, orig_fpcr;
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uint64_t swcr, fpcr, orig_fpcr;
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if (get_user_u64 (swcr, arg2))
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if (get_user_u64 (swcr, arg2)) {
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goto efault;
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goto efault;
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orig_fpcr = cpu_alpha_load_fpcr (cpu_env);
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}
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orig_fpcr = cpu_alpha_load_fpcr(cpu_env);
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fpcr = orig_fpcr & FPCR_DYN_MASK;
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fpcr = orig_fpcr & FPCR_DYN_MASK;
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/* Copied from linux ieee_swcr_to_fpcr. */
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/* Copied from linux ieee_swcr_to_fpcr. */
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@ -7719,16 +7719,57 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
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fpcr |= (swcr & SWCR_MAP_UMZ ? FPCR_UNDZ | FPCR_UNFD : 0);
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fpcr |= (swcr & SWCR_MAP_UMZ ? FPCR_UNDZ | FPCR_UNFD : 0);
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fpcr |= (~swcr & SWCR_TRAP_ENABLE_DNO) << 41;
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fpcr |= (~swcr & SWCR_TRAP_ENABLE_DNO) << 41;
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cpu_alpha_store_fpcr (cpu_env, fpcr);
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cpu_alpha_store_fpcr(cpu_env, fpcr);
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ret = 0;
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}
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break;
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case TARGET_SSI_IEEE_RAISE_EXCEPTION:
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{
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uint64_t exc, fpcr, orig_fpcr;
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int si_code;
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if (get_user_u64(exc, arg2)) {
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goto efault;
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}
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orig_fpcr = cpu_alpha_load_fpcr(cpu_env);
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/* We only add to the exception status here. */
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fpcr = orig_fpcr | ((exc & SWCR_STATUS_MASK) << 35);
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cpu_alpha_store_fpcr(cpu_env, fpcr);
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ret = 0;
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ret = 0;
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if (arg1 == TARGET_SSI_IEEE_RAISE_EXCEPTION) {
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/* Old exceptions are not signaled. */
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/* Old exceptions are not signaled. */
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fpcr &= ~(orig_fpcr & FPCR_STATUS_MASK);
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fpcr &= ~(orig_fpcr & FPCR_STATUS_MASK);
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/* If any exceptions set by this call, and are unmasked,
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/* If any exceptions set by this call,
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send a signal. */
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and are unmasked, send a signal. */
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/* ??? FIXME */
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si_code = 0;
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if ((fpcr & (FPCR_INE | FPCR_INED)) == FPCR_INE) {
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si_code = TARGET_FPE_FLTRES;
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}
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if ((fpcr & (FPCR_UNF | FPCR_UNFD)) == FPCR_UNF) {
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si_code = TARGET_FPE_FLTUND;
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}
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if ((fpcr & (FPCR_OVF | FPCR_OVFD)) == FPCR_OVF) {
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si_code = TARGET_FPE_FLTOVF;
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}
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if ((fpcr & (FPCR_DZE | FPCR_DZED)) == FPCR_DZE) {
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si_code = TARGET_FPE_FLTDIV;
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}
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if ((fpcr & (FPCR_INV | FPCR_INVD)) == FPCR_INV) {
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si_code = TARGET_FPE_FLTINV;
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}
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if (si_code != 0) {
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target_siginfo_t info;
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info.si_signo = SIGFPE;
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info.si_errno = 0;
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info.si_code = si_code;
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info._sifields._sigfault._addr
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= ((CPUArchState *)cpu_env)->pc;
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queue_signal((CPUArchState *)cpu_env, info.si_signo, &info);
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}
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}
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}
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}
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break;
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break;
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