mirror of https://github.com/xemu-project/xemu.git
openpic: rename openpic_t to OpenPICState
Rename the openpic_t struct to OpenPICState, so it adheres better to the current coding style rules. Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Alexander Graf
parent
1945dbc15f
commit
6d544ee8ac
68
hw/openpic.c
68
hw/openpic.c
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@ -204,7 +204,7 @@ typedef struct IRQ_dst_t {
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qemu_irq *irqs;
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} IRQ_dst_t;
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typedef struct openpic_t {
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typedef struct OpenPICState {
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PCIDevice pci_dev;
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MemoryRegion mem;
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@ -242,9 +242,9 @@ typedef struct openpic_t {
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int max_irq;
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int irq_ipi0;
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int irq_tim0;
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} openpic_t;
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} OpenPICState;
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static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src);
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static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src);
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static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ)
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{
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@ -261,7 +261,7 @@ static inline int IRQ_testbit (IRQ_queue_t *q, int n_IRQ)
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return test_bit(q->queue, n_IRQ);
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}
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static void IRQ_check (openpic_t *opp, IRQ_queue_t *q)
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static void IRQ_check(OpenPICState *opp, IRQ_queue_t *q)
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{
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int next, i;
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int priority;
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@ -282,7 +282,7 @@ static void IRQ_check (openpic_t *opp, IRQ_queue_t *q)
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q->priority = priority;
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}
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static int IRQ_get_next (openpic_t *opp, IRQ_queue_t *q)
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static int IRQ_get_next(OpenPICState *opp, IRQ_queue_t *q)
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{
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if (q->next == -1) {
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/* XXX: optimize */
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@ -292,7 +292,7 @@ static int IRQ_get_next (openpic_t *opp, IRQ_queue_t *q)
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return q->next;
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}
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static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int n_IRQ)
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static void IRQ_local_pipe(OpenPICState *opp, int n_CPU, int n_IRQ)
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{
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IRQ_dst_t *dst;
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IRQ_src_t *src;
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@ -334,7 +334,7 @@ static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int n_IRQ)
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}
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/* update pic state because registers for n_IRQ have changed value */
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static void openpic_update_irq(openpic_t *opp, int n_IRQ)
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static void openpic_update_irq(OpenPICState *opp, int n_IRQ)
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{
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IRQ_src_t *src;
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int i;
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@ -393,7 +393,7 @@ static void openpic_update_irq(openpic_t *opp, int n_IRQ)
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static void openpic_set_irq(void *opaque, int n_IRQ, int level)
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{
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openpic_t *opp = opaque;
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OpenPICState *opp = opaque;
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IRQ_src_t *src;
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src = &opp->src[n_IRQ];
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@ -415,7 +415,7 @@ static void openpic_set_irq(void *opaque, int n_IRQ, int level)
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static void openpic_reset (void *opaque)
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{
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openpic_t *opp = (openpic_t *)opaque;
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OpenPICState *opp = (OpenPICState *)opaque;
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int i;
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opp->glbc = 0x80000000;
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@ -450,17 +450,17 @@ static void openpic_reset (void *opaque)
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opp->glbc = 0x00000000;
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}
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static inline uint32_t read_IRQreg_ide(openpic_t *opp, int n_IRQ)
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static inline uint32_t read_IRQreg_ide(OpenPICState *opp, int n_IRQ)
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{
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return opp->src[n_IRQ].ide;
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}
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static inline uint32_t read_IRQreg_ipvp(openpic_t *opp, int n_IRQ)
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static inline uint32_t read_IRQreg_ipvp(OpenPICState *opp, int n_IRQ)
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{
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return opp->src[n_IRQ].ipvp;
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}
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static inline void write_IRQreg_ide(openpic_t *opp, int n_IRQ, uint32_t val)
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static inline void write_IRQreg_ide(OpenPICState *opp, int n_IRQ, uint32_t val)
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{
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uint32_t tmp;
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@ -470,7 +470,7 @@ static inline void write_IRQreg_ide(openpic_t *opp, int n_IRQ, uint32_t val)
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DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ide);
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}
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static inline void write_IRQreg_ipvp(openpic_t *opp, int n_IRQ, uint32_t val)
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static inline void write_IRQreg_ipvp(OpenPICState *opp, int n_IRQ, uint32_t val)
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{
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/* NOTE: not fully accurate for special IRQs, but simple and sufficient */
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/* ACTIVITY bit is read-only */
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@ -484,7 +484,7 @@ static inline void write_IRQreg_ipvp(openpic_t *opp, int n_IRQ, uint32_t val)
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static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned len)
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{
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openpic_t *opp = opaque;
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OpenPICState *opp = opaque;
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IRQ_dst_t *dst;
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int idx;
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@ -547,7 +547,7 @@ static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
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static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len)
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{
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openpic_t *opp = opaque;
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OpenPICState *opp = opaque;
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uint32_t retval;
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DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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@ -599,10 +599,10 @@ static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len)
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return retval;
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}
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static void openpic_timer_write(void *opaque, hwaddr addr, uint64_t val,
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static void openpic_tmr_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned len)
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{
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openpic_t *opp = opaque;
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OpenPICState *opp = opaque;
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int idx;
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DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
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@ -635,9 +635,9 @@ static void openpic_timer_write(void *opaque, hwaddr addr, uint64_t val,
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}
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}
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static uint64_t openpic_timer_read(void *opaque, hwaddr addr, unsigned len)
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static uint64_t openpic_tmr_read(void *opaque, hwaddr addr, unsigned len)
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{
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openpic_t *opp = opaque;
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OpenPICState *opp = opaque;
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uint32_t retval = -1;
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int idx;
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@ -675,7 +675,7 @@ out:
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static void openpic_src_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned len)
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{
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openpic_t *opp = opaque;
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OpenPICState *opp = opaque;
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int idx;
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DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
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@ -694,7 +694,7 @@ static void openpic_src_write(void *opaque, hwaddr addr, uint64_t val,
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static uint64_t openpic_src_read(void *opaque, uint64_t addr, unsigned len)
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{
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openpic_t *opp = opaque;
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OpenPICState *opp = opaque;
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uint32_t retval;
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int idx;
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@ -719,7 +719,7 @@ static uint64_t openpic_src_read(void *opaque, uint64_t addr, unsigned len)
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static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
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uint32_t val, int idx)
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{
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openpic_t *opp = opaque;
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OpenPICState *opp = opaque;
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IRQ_src_t *src;
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IRQ_dst_t *dst;
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int s_IRQ, n_IRQ;
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@ -783,7 +783,7 @@ static void openpic_cpu_write(void *opaque, hwaddr addr, uint64_t val,
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static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
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int idx)
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{
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openpic_t *opp = opaque;
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OpenPICState *opp = opaque;
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IRQ_src_t *src;
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IRQ_dst_t *dst;
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uint32_t retval;
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@ -885,8 +885,8 @@ static const MemoryRegionOps openpic_glb_ops_be = {
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};
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static const MemoryRegionOps openpic_tmr_ops_le = {
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.write = openpic_timer_write,
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.read = openpic_timer_read,
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.write = openpic_tmr_write,
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.read = openpic_tmr_read,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 4,
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@ -895,8 +895,8 @@ static const MemoryRegionOps openpic_tmr_ops_le = {
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};
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static const MemoryRegionOps openpic_tmr_ops_be = {
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.write = openpic_timer_write,
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.read = openpic_timer_read,
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.write = openpic_tmr_write,
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.read = openpic_tmr_read,
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.endianness = DEVICE_BIG_ENDIAN,
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.impl = {
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.min_access_size = 4,
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@ -957,7 +957,7 @@ static void openpic_save_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
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static void openpic_save(QEMUFile* f, void *opaque)
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{
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openpic_t *opp = (openpic_t *)opaque;
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OpenPICState *opp = (OpenPICState *)opaque;
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unsigned int i;
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qemu_put_be32s(f, &opp->glbc);
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@ -1003,7 +1003,7 @@ static void openpic_load_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
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static int openpic_load(QEMUFile* f, void *opaque, int version_id)
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{
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openpic_t *opp = (openpic_t *)opaque;
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OpenPICState *opp = (OpenPICState *)opaque;
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unsigned int i;
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if (version_id != 1)
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@ -1039,7 +1039,7 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
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return pci_device_load(&opp->pci_dev, f);
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}
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static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src)
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static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src)
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{
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int n_ci = IDR_CI0_SHIFT - n_CPU;
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@ -1053,7 +1053,7 @@ static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src)
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qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
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qemu_irq **irqs, qemu_irq irq_out)
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{
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openpic_t *opp;
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OpenPICState *opp;
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int i;
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struct {
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const char *name;
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@ -1074,7 +1074,7 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
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/* XXX: for now, only one CPU is supported */
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if (nb_cpus != 1)
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return NULL;
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opp = g_malloc0(sizeof(openpic_t));
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opp = g_malloc0(sizeof(OpenPICState));
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memory_region_init(&opp->mem, "openpic", 0x40000);
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@ -1115,7 +1115,7 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
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qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
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int nb_cpus, qemu_irq **irqs, qemu_irq irq_out)
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{
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openpic_t *mpp;
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OpenPICState *mpp;
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int i;
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struct {
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const char *name;
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@ -1129,7 +1129,7 @@ qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
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{"cpu", &openpic_cpu_ops_be, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE},
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};
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mpp = g_malloc0(sizeof(openpic_t));
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mpp = g_malloc0(sizeof(OpenPICState));
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memory_region_init(&mpp->mem, "mpic", 0x40000);
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memory_region_add_subregion(address_space, base, &mpp->mem);
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