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target/riscv: Add cycle & instret privilege mode filtering definitions 

This adds the definitions for ISA extension smcntrpmf.

Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20240711-smcntrpmf_v7-v8-4-b7c38ae7b263@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Kaiwen Xue 2024-07-11 15:31:07 -07:00 committed by Alistair Francis
parent 251dccc09a
commit 6d1e3893cf
2 changed files with 35 additions and 0 deletions
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6
target/riscv/cpu.h
View File

@ -362,6 +362,12 @@ struct CPUArchState {
uint32_t mcountinhibit;
/* PMU cycle & instret privilege mode filtering */
target_ulong mcyclecfg;
target_ulong mcyclecfgh;
target_ulong minstretcfg;
target_ulong minstretcfgh;
/* PMU counter state */
PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS];

29
target/riscv/cpu_bits.h
View File

@ -397,6 +397,10 @@
/* Machine counter-inhibit register */
#define CSR_MCOUNTINHIBIT 0x320
/* Machine counter configuration registers */
#define CSR_MCYCLECFG 0x321
#define CSR_MINSTRETCFG 0x322
#define CSR_MHPMEVENT3 0x323
#define CSR_MHPMEVENT4 0x324
#define CSR_MHPMEVENT5 0x325
@ -427,6 +431,9 @@
#define CSR_MHPMEVENT30 0x33e
#define CSR_MHPMEVENT31 0x33f
#define CSR_MCYCLECFGH 0x721
#define CSR_MINSTRETCFGH 0x722
#define CSR_MHPMEVENT3H 0x723
#define CSR_MHPMEVENT4H 0x724
#define CSR_MHPMEVENT5H 0x725
@ -884,6 +891,28 @@ typedef enum RISCVException {
/* PMU related bits */
#define MIE_LCOFIE (1 << IRQ_PMU_OVF)
#define MCYCLECFG_BIT_MINH BIT_ULL(62)
#define MCYCLECFGH_BIT_MINH BIT(30)
#define MCYCLECFG_BIT_SINH BIT_ULL(61)
#define MCYCLECFGH_BIT_SINH BIT(29)
#define MCYCLECFG_BIT_UINH BIT_ULL(60)
#define MCYCLECFGH_BIT_UINH BIT(28)
#define MCYCLECFG_BIT_VSINH BIT_ULL(59)
#define MCYCLECFGH_BIT_VSINH BIT(27)
#define MCYCLECFG_BIT_VUINH BIT_ULL(58)
#define MCYCLECFGH_BIT_VUINH BIT(26)
#define MINSTRETCFG_BIT_MINH BIT_ULL(62)
#define MINSTRETCFGH_BIT_MINH BIT(30)
#define MINSTRETCFG_BIT_SINH BIT_ULL(61)
#define MINSTRETCFGH_BIT_SINH BIT(29)
#define MINSTRETCFG_BIT_UINH BIT_ULL(60)
#define MINSTRETCFGH_BIT_UINH BIT(28)
#define MINSTRETCFG_BIT_VSINH BIT_ULL(59)
#define MINSTRETCFGH_BIT_VSINH BIT(27)
#define MINSTRETCFG_BIT_VUINH BIT_ULL(58)
#define MINSTRETCFGH_BIT_VUINH BIT(26)
#define MHPMEVENT_BIT_OF BIT_ULL(63)
#define MHPMEVENTH_BIT_OF BIT(31)
#define MHPMEVENT_BIT_MINH BIT_ULL(62)