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target/riscv: fix a typo with interrupt names 

Interrupt names have been swapped in 205377f8 and do not follow
IRQ_*_EXT definition order.

Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210421133236.11323-1-emmanuel.blot@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Emmanuel Blot 2021-04-21 15:32:36 +02:00 committed by Alistair Francis
parent 3a7f7757ba
commit 6cfcf77573
1 changed files with 1 additions and 1 deletions
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2
target/riscv/cpu.c
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@ -88,8 +88,8 @@ const char * const riscv_intr_names[] = {
"vs_timer",
"m_timer",
"u_external",
"s_external",
"vs_external",
"h_external",
"m_external",
"reserved",
"reserved",