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target/riscv: correct "code should not be reached" for x-rv128 

The addition of uxl support in gdbstub adds a few checks on the maximum
register length, but omitted MXL_RV128, an experimental feature.
This patch makes rv128 react as rv64, as previously.

Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220124202456.420258-1-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frédéric Pétrot 2022-01-24 21:24:56 +01:00 committed by Alistair Francis
parent f42483d776
commit 6c3a924725
2 changed files with 4 additions and 2 deletions
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3
target/riscv/cpu.c
View File

@ -528,9 +528,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
switch (env->misa_mxl_max) { switch (env->misa_mxl_max) {
#ifdef TARGET_RISCV64 #ifdef TARGET_RISCV64
case MXL_RV64: case MXL_RV64:
cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
break;
case MXL_RV128: case MXL_RV128:
cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
break; break;
#endif #endif
case MXL_RV32: case MXL_RV32:

3
target/riscv/gdbstub.c
View File

@ -64,6 +64,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
case MXL_RV32: case MXL_RV32:
return gdb_get_reg32(mem_buf, tmp); return gdb_get_reg32(mem_buf, tmp);
case MXL_RV64: case MXL_RV64:
case MXL_RV128:
return gdb_get_reg64(mem_buf, tmp); return gdb_get_reg64(mem_buf, tmp);
default: default:
g_assert_not_reached(); g_assert_not_reached();
@ -84,6 +85,7 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
length = 4; length = 4;
break; break;
case MXL_RV64: case MXL_RV64:
case MXL_RV128:
if (env->xl < MXL_RV64) { if (env->xl < MXL_RV64) {
tmp = (int32_t)ldq_p(mem_buf); tmp = (int32_t)ldq_p(mem_buf);
} else { } else {
@ -420,6 +422,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
1, "riscv-32bit-virtual.xml", 0); 1, "riscv-32bit-virtual.xml", 0);
break; break;
case MXL_RV64: case MXL_RV64:
case MXL_RV128:
gdb_register_coprocessor(cs, riscv_gdb_get_virtual, gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
riscv_gdb_set_virtual, riscv_gdb_set_virtual,
1, "riscv-64bit-virtual.xml", 0); 1, "riscv-64bit-virtual.xml", 0);