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target/arm: Determine final stage 2 output PA space based on original IPA
As per the AArch64.S2Walk() pseudo-code in the ARMv8 ARM, the final decision as to the output address's PA space based on the SA/SW/NSA/NSW bits needs to take the input IPA's PA space into account, and not the PA space of the result of the stage 2 walk itself. Signed-off-by: Idan Horowitz <idan.horowitz@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220327093427.1548629-4-idan.horowitz@gmail.com [PMM: fixed commit message typo] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -12644,6 +12644,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
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hwaddr ipa;
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hwaddr ipa;
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int s2_prot;
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int s2_prot;
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int ret;
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int ret;
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bool ipa_secure;
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ARMCacheAttrs cacheattrs2 = {};
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ARMCacheAttrs cacheattrs2 = {};
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ARMMMUIdx s2_mmu_idx;
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ARMMMUIdx s2_mmu_idx;
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bool is_el0;
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bool is_el0;
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@ -12657,14 +12658,15 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
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return ret;
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return ret;
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}
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}
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ipa_secure = attrs->secure;
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if (arm_is_secure_below_el3(env)) {
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if (arm_is_secure_below_el3(env)) {
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if (attrs->secure) {
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if (ipa_secure) {
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attrs->secure = !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW);
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attrs->secure = !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW);
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} else {
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} else {
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attrs->secure = !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW);
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attrs->secure = !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW);
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}
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}
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} else {
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} else {
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assert(!attrs->secure);
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assert(!ipa_secure);
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}
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}
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s2_mmu_idx = attrs->secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
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s2_mmu_idx = attrs->secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
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@ -12701,7 +12703,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
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/* Check if IPA translates to secure or non-secure PA space. */
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/* Check if IPA translates to secure or non-secure PA space. */
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if (arm_is_secure_below_el3(env)) {
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if (arm_is_secure_below_el3(env)) {
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if (attrs->secure) {
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if (ipa_secure) {
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attrs->secure =
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attrs->secure =
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!(env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW));
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!(env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW));
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} else {
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} else {
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