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accel/tcg: Rename tlb_flush_page_bits -> range]_by_mmuidx_async_0 

Rename to match tlb_flush_range_locked.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210509151618.2331764-8-f4bug@amsat.org
Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org>
[PMD: Split from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2021-05-09 17:16:16 +02:00 committed by Peter Maydell
parent c13b27d826
commit 6be48e45ac
1 changed files with 5 additions and 6 deletions
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11
accel/tcg/cputlb.c
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@ -764,9 +764,8 @@ typedef struct {
uint16_t bits; uint16_t bits;
} TLBFlushRangeData; } TLBFlushRangeData;
static void static void tlb_flush_range_by_mmuidx_async_0(CPUState *cpu,
tlb_flush_page_bits_by_mmuidx_async_0(CPUState *cpu, TLBFlushRangeData d)
TLBFlushRangeData d)
{ {
CPUArchState *env = cpu->env_ptr; CPUArchState *env = cpu->env_ptr;
int mmu_idx; int mmu_idx;
@ -793,7 +792,7 @@ static void tlb_flush_page_bits_by_mmuidx_async_2(CPUState *cpu,
run_on_cpu_data data) run_on_cpu_data data)
{ {
TLBFlushRangeData *d = data.host_ptr; TLBFlushRangeData *d = data.host_ptr;
tlb_flush_page_bits_by_mmuidx_async_0(cpu, *d); tlb_flush_range_by_mmuidx_async_0(cpu, *d);
g_free(d); g_free(d);
} }
@ -824,7 +823,7 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr,
d.bits = bits; d.bits = bits;
if (qemu_cpu_is_self(cpu)) { if (qemu_cpu_is_self(cpu)) {
tlb_flush_page_bits_by_mmuidx_async_0(cpu, d); tlb_flush_range_by_mmuidx_async_0(cpu, d);
} else { } else {
/* Otherwise allocate a structure, freed by the worker. */ /* Otherwise allocate a structure, freed by the worker. */
TLBFlushRangeData *p = g_memdup(&d, sizeof(d)); TLBFlushRangeData *p = g_memdup(&d, sizeof(d));
@ -876,7 +875,7 @@ void tlb_flush_range_by_mmuidx_all_cpus(CPUState *src_cpu,
} }
} }
tlb_flush_page_bits_by_mmuidx_async_0(src_cpu, d); tlb_flush_range_by_mmuidx_async_0(src_cpu, d);
} }
void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *src_cpu, void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *src_cpu,