From 6bc3dfa96de4173b12929824eaf80fc95d22ac28 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:55:57 +0800 Subject: [PATCH] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers If VS field is off, accessing vector csr registers should raise an illegal-instruction exception. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-12-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5d1eec1ea0..3dfbc17738 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -48,6 +48,11 @@ static RISCVException fs(CPURISCVState *env, int csrno) static RISCVException vs(CPURISCVState *env, int csrno) { if (env->misa_ext & RVV) { +#if !defined(CONFIG_USER_ONLY) + if (!env->debugger && !riscv_cpu_vector_enabled(env)) { + return RISCV_EXCP_ILLEGAL_INST; + } +#endif return RISCV_EXCP_NONE; } return RISCV_EXCP_ILLEGAL_INST;