ShuriZma
/
xemu
mirror of https://github.com/xemu-project/xemu.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

target/nios2 : Explicitly ask for target-endian loads and stores 

When we generate code for guest loads and stores, at the moment they
end up being requests for a host-endian access. So for target-system-nios2
(little endian) a load like
   ldw        r3,0(r4)
results on an x86 host in the TCG IR
   qemu_ld_a32_i32 r3,loc2,al+leul,0
but on s390 it is
   qemu_ld_a32_i32 r3,loc2,al+beul,0

The result is that guests don't work on big-endian hosts.

Use the MO_TE* memops rather than the plain ones.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1693
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230623172556.1951974-1-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Peter Maydell 2023-06-23 18:25:56 +01:00 committed by Richard Henderson
parent ec2297bda2
commit 6ab1790226
1 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
target/nios2/translate.c
View File

@ -436,19 +436,19 @@ static const Nios2Instruction i_type_instructions[] = {
INSTRUCTION_FLG(gen_cmpxxsi, TCG_COND_GE), /* cmpgei */ INSTRUCTION_FLG(gen_cmpxxsi, TCG_COND_GE), /* cmpgei */
INSTRUCTION_ILLEGAL(), INSTRUCTION_ILLEGAL(),
INSTRUCTION_ILLEGAL(), INSTRUCTION_ILLEGAL(),
INSTRUCTION_FLG(gen_ldx, MO_UW), /* ldhu */ INSTRUCTION_FLG(gen_ldx, MO_TEUW), /* ldhu */
INSTRUCTION(andi), /* andi */ INSTRUCTION(andi), /* andi */
INSTRUCTION_FLG(gen_stx, MO_UW), /* sth */ INSTRUCTION_FLG(gen_stx, MO_TEUW), /* sth */
INSTRUCTION_FLG(gen_bxx, TCG_COND_GE), /* bge */ INSTRUCTION_FLG(gen_bxx, TCG_COND_GE), /* bge */
INSTRUCTION_FLG(gen_ldx, MO_SW), /* ldh */ INSTRUCTION_FLG(gen_ldx, MO_TESW), /* ldh */
INSTRUCTION_FLG(gen_cmpxxsi, TCG_COND_LT), /* cmplti */ INSTRUCTION_FLG(gen_cmpxxsi, TCG_COND_LT), /* cmplti */
INSTRUCTION_ILLEGAL(), INSTRUCTION_ILLEGAL(),
INSTRUCTION_ILLEGAL(), INSTRUCTION_ILLEGAL(),
INSTRUCTION_NOP(), /* initda */ INSTRUCTION_NOP(), /* initda */
INSTRUCTION(ori), /* ori */ INSTRUCTION(ori), /* ori */
INSTRUCTION_FLG(gen_stx, MO_UL), /* stw */ INSTRUCTION_FLG(gen_stx, MO_TEUL), /* stw */
INSTRUCTION_FLG(gen_bxx, TCG_COND_LT), /* blt */ INSTRUCTION_FLG(gen_bxx, TCG_COND_LT), /* blt */
INSTRUCTION_FLG(gen_ldx, MO_UL), /* ldw */ INSTRUCTION_FLG(gen_ldx, MO_TEUL), /* ldw */
INSTRUCTION_FLG(gen_cmpxxsi, TCG_COND_NE), /* cmpnei */ INSTRUCTION_FLG(gen_cmpxxsi, TCG_COND_NE), /* cmpnei */
INSTRUCTION_ILLEGAL(), INSTRUCTION_ILLEGAL(),
INSTRUCTION_ILLEGAL(), INSTRUCTION_ILLEGAL(),
@ -468,19 +468,19 @@ static const Nios2Instruction i_type_instructions[] = {
INSTRUCTION_FLG(gen_cmpxxui, TCG_COND_GEU), /* cmpgeui */ INSTRUCTION_FLG(gen_cmpxxui, TCG_COND_GEU), /* cmpgeui */
INSTRUCTION_ILLEGAL(), INSTRUCTION_ILLEGAL(),
INSTRUCTION_ILLEGAL(), INSTRUCTION_ILLEGAL(),
INSTRUCTION_FLG(gen_ldx, MO_UW), /* ldhuio */ INSTRUCTION_FLG(gen_ldx, MO_TEUW), /* ldhuio */
INSTRUCTION(andhi), /* andhi */ INSTRUCTION(andhi), /* andhi */
INSTRUCTION_FLG(gen_stx, MO_UW), /* sthio */ INSTRUCTION_FLG(gen_stx, MO_TEUW), /* sthio */
INSTRUCTION_FLG(gen_bxx, TCG_COND_GEU), /* bgeu */ INSTRUCTION_FLG(gen_bxx, TCG_COND_GEU), /* bgeu */
INSTRUCTION_FLG(gen_ldx, MO_SW), /* ldhio */ INSTRUCTION_FLG(gen_ldx, MO_TESW), /* ldhio */
INSTRUCTION_FLG(gen_cmpxxui, TCG_COND_LTU), /* cmpltui */ INSTRUCTION_FLG(gen_cmpxxui, TCG_COND_LTU), /* cmpltui */
INSTRUCTION_ILLEGAL(), INSTRUCTION_ILLEGAL(),
INSTRUCTION_UNIMPLEMENTED(), /* custom */ INSTRUCTION_UNIMPLEMENTED(), /* custom */
INSTRUCTION_NOP(), /* initd */ INSTRUCTION_NOP(), /* initd */
INSTRUCTION(orhi), /* orhi */ INSTRUCTION(orhi), /* orhi */
INSTRUCTION_FLG(gen_stx, MO_SL), /* stwio */ INSTRUCTION_FLG(gen_stx, MO_TESL), /* stwio */
INSTRUCTION_FLG(gen_bxx, TCG_COND_LTU), /* bltu */ INSTRUCTION_FLG(gen_bxx, TCG_COND_LTU), /* bltu */
INSTRUCTION_FLG(gen_ldx, MO_UL), /* ldwio */ INSTRUCTION_FLG(gen_ldx, MO_TEUL), /* ldwio */
INSTRUCTION(rdprs), /* rdprs */ INSTRUCTION(rdprs), /* rdprs */
INSTRUCTION_ILLEGAL(), INSTRUCTION_ILLEGAL(),
INSTRUCTION_FLG(handle_r_type_instr, 0), /* R-Type */ INSTRUCTION_FLG(handle_r_type_instr, 0), /* R-Type */