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target/arm: Use new FPCR_NZCV_MASK constant 

We defined a constant name for the mask of NZCV bits in the FPCR/FPSCR
in the previous commit; use it in a couple of places in existing code,
where we're masking out everything except NZCV for the "load to Rt=15
sets CPSR.NZCV" special case.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-12-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2020-11-19 21:56:00 +00:00
parent 9542c30bcf
commit 6a017acdf8
1 changed files with 2 additions and 2 deletions
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4
target/arm/translate-vfp.c.inc
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@ -744,7 +744,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
* helper call for the "VMRS to CPSR.NZCV" insn. * helper call for the "VMRS to CPSR.NZCV" insn.
*/ */
tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
tcg_gen_andi_i32(tmp, tmp, 0xf0000000); tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
storefn(s, opaque, tmp); storefn(s, opaque, tmp);
break; break;
default: default:
@ -885,7 +885,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
case ARM_VFP_FPSCR: case ARM_VFP_FPSCR:
if (a->rt == 15) { if (a->rt == 15) {
tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
tcg_gen_andi_i32(tmp, tmp, 0xf0000000); tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
} else { } else {
tmp = tcg_temp_new_i32(); tmp = tcg_temp_new_i32();
gen_helper_vfp_get_fpscr(tmp, cpu_env); gen_helper_vfp_get_fpscr(tmp, cpu_env);