From 4a9b31b82bcd2cafe85137334f1c07afe56cc224 Mon Sep 17 00:00:00 2001 From: Dayeol Lee Date: Fri, 26 Oct 2018 18:04:27 +0000 Subject: [PATCH 1/3] target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64 pmp_read_cfg() returns 8-bit value, which is combined together to form a single pmpcfg CSR. The default promotion rules will result in an integer here ("i*8" is integer, which flows through) resulting in a 32-bit signed value on most hosts. That's bogus on RV64I, with the high bits of the CSR being wrong. Signed-off-by: Dayeol Lee Reviewed-by: Palmer Dabbelt Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/pmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index f432f3b759..03abd8fe5e 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -325,7 +325,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index) { int i; target_ulong cfg_val = 0; - uint8_t val = 0; + target_ulong val = 0; for (i = 0; i < sizeof(target_ulong); i++) { val = pmp_read_cfg(env, (reg_index * sizeof(target_ulong)) + i); From a17a61f306c12690d541515798b2d227049aa35b Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Mon, 29 Oct 2018 09:06:44 -0700 Subject: [PATCH 2/3] Add Alistair as a RISC-V Maintainer Alistair has been contributing to the RISC-V QEMU port for a while now so I'd like him to be officially listed as a maintainer. I've checked with the other RISC-V maintainers and there are no objections, and I've also checked with Alistair so he knows I'm volunteering him. Signed-off-by: Palmer Dabbelt --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index d794bd7a66..d550fd8b80 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -241,6 +241,7 @@ F: disas/ppc.c RISC-V M: Michael Clark M: Palmer Dabbelt +M: Alistair Francis M: Sagar Karandikar M: Bastian Koppelmann S: Maintained From a094b3544f2855c0489f5df3c938b14b9a5899e5 Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Tue, 30 Oct 2018 09:19:05 -0700 Subject: [PATCH 3/3] Add qemu-riscv@nongnu.org as the RISC-V list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We now have a RISC-V specific QEMU development list. Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Palmer Dabbelt --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index d550fd8b80..10983bd52d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -244,6 +244,7 @@ M: Palmer Dabbelt M: Alistair Francis M: Sagar Karandikar M: Bastian Koppelmann +L: qemu-riscv@nongnu.org S: Maintained F: target/riscv/ F: hw/riscv/