mirror of https://github.com/xemu-project/xemu.git
target/arm: Convert FNMUL to decodetree
This is the last instruction within disas_fp_2src, so remove that and its subroutines. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-24-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
21e885aff4
commit
69cefabcac
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@ -703,6 +703,7 @@ FADD_s 0001 1110 ..1 ..... 0010 10 ..... ..... @rrr_hsd
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FSUB_s 0001 1110 ..1 ..... 0011 10 ..... ..... @rrr_hsd
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FDIV_s 0001 1110 ..1 ..... 0001 10 ..... ..... @rrr_hsd
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FMUL_s 0001 1110 ..1 ..... 0000 10 ..... ..... @rrr_hsd
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FNMUL_s 0001 1110 ..1 ..... 1000 10 ..... ..... @rrr_hsd
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FMAX_s 0001 1110 ..1 ..... 0100 10 ..... ..... @rrr_hsd
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FMIN_s 0001 1110 ..1 ..... 0101 10 ..... ..... @rrr_hsd
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@ -4950,6 +4950,31 @@ static const FPScalar f_scalar_fmulx = {
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};
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TRANS(FMULX_s, do_fp3_scalar, a, &f_scalar_fmulx)
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static void gen_fnmul_h(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, TCGv_ptr s)
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{
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gen_helper_vfp_mulh(d, n, m, s);
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gen_vfp_negh(d, d);
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}
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static void gen_fnmul_s(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, TCGv_ptr s)
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{
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gen_helper_vfp_muls(d, n, m, s);
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gen_vfp_negs(d, d);
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}
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static void gen_fnmul_d(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_ptr s)
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{
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gen_helper_vfp_muld(d, n, m, s);
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gen_vfp_negd(d, d);
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}
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static const FPScalar f_scalar_fnmul = {
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gen_fnmul_h,
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gen_fnmul_s,
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gen_fnmul_d,
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};
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TRANS(FNMUL_s, do_fp3_scalar, a, &f_scalar_fnmul)
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static bool do_fp3_vector(DisasContext *s, arg_qrrr_e *a,
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gen_helper_gvec_3_ptr * const fns[3])
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{
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@ -6932,156 +6957,6 @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
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}
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}
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/* Floating-point data-processing (2 source) - single precision */
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static void handle_fp_2src_single(DisasContext *s, int opcode,
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int rd, int rn, int rm)
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{
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TCGv_i32 tcg_op1;
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TCGv_i32 tcg_op2;
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TCGv_i32 tcg_res;
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TCGv_ptr fpst;
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tcg_res = tcg_temp_new_i32();
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fpst = fpstatus_ptr(FPST_FPCR);
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tcg_op1 = read_fp_sreg(s, rn);
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tcg_op2 = read_fp_sreg(s, rm);
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switch (opcode) {
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case 0x8: /* FNMUL */
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gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst);
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gen_vfp_negs(tcg_res, tcg_res);
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break;
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default:
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case 0x0: /* FMUL */
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case 0x1: /* FDIV */
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case 0x2: /* FADD */
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case 0x3: /* FSUB */
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case 0x4: /* FMAX */
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case 0x5: /* FMIN */
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case 0x6: /* FMAXNM */
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case 0x7: /* FMINNM */
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g_assert_not_reached();
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}
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write_fp_sreg(s, rd, tcg_res);
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}
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/* Floating-point data-processing (2 source) - double precision */
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static void handle_fp_2src_double(DisasContext *s, int opcode,
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int rd, int rn, int rm)
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{
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TCGv_i64 tcg_op1;
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TCGv_i64 tcg_op2;
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TCGv_i64 tcg_res;
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TCGv_ptr fpst;
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tcg_res = tcg_temp_new_i64();
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fpst = fpstatus_ptr(FPST_FPCR);
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tcg_op1 = read_fp_dreg(s, rn);
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tcg_op2 = read_fp_dreg(s, rm);
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switch (opcode) {
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case 0x8: /* FNMUL */
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gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst);
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gen_vfp_negd(tcg_res, tcg_res);
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break;
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default:
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case 0x0: /* FMUL */
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case 0x1: /* FDIV */
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case 0x2: /* FADD */
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case 0x3: /* FSUB */
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case 0x4: /* FMAX */
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case 0x5: /* FMIN */
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case 0x6: /* FMAXNM */
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case 0x7: /* FMINNM */
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g_assert_not_reached();
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}
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write_fp_dreg(s, rd, tcg_res);
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}
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/* Floating-point data-processing (2 source) - half precision */
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static void handle_fp_2src_half(DisasContext *s, int opcode,
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int rd, int rn, int rm)
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{
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TCGv_i32 tcg_op1;
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TCGv_i32 tcg_op2;
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TCGv_i32 tcg_res;
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TCGv_ptr fpst;
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tcg_res = tcg_temp_new_i32();
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fpst = fpstatus_ptr(FPST_FPCR_F16);
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tcg_op1 = read_fp_hreg(s, rn);
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tcg_op2 = read_fp_hreg(s, rm);
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switch (opcode) {
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case 0x8: /* FNMUL */
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gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
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gen_vfp_negh(tcg_res, tcg_res);
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break;
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default:
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case 0x0: /* FMUL */
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case 0x1: /* FDIV */
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case 0x2: /* FADD */
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case 0x3: /* FSUB */
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case 0x4: /* FMAX */
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case 0x5: /* FMIN */
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case 0x6: /* FMAXNM */
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case 0x7: /* FMINNM */
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g_assert_not_reached();
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}
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write_fp_sreg(s, rd, tcg_res);
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}
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/* Floating point data-processing (2 source)
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* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
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* +---+---+---+-----------+------+---+------+--------+-----+------+------+
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* | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
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* +---+---+---+-----------+------+---+------+--------+-----+------+------+
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*/
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static void disas_fp_2src(DisasContext *s, uint32_t insn)
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{
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int mos = extract32(insn, 29, 3);
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int type = extract32(insn, 22, 2);
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int rd = extract32(insn, 0, 5);
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int rn = extract32(insn, 5, 5);
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int rm = extract32(insn, 16, 5);
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int opcode = extract32(insn, 12, 4);
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if (opcode > 8 || mos) {
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unallocated_encoding(s);
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return;
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}
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switch (type) {
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case 0:
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if (!fp_access_check(s)) {
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return;
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}
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handle_fp_2src_single(s, opcode, rd, rn, rm);
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break;
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case 1:
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if (!fp_access_check(s)) {
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return;
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}
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handle_fp_2src_double(s, opcode, rd, rn, rm);
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break;
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case 3:
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if (!dc_isar_feature(aa64_fp16, s)) {
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unallocated_encoding(s);
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return;
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}
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if (!fp_access_check(s)) {
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return;
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}
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handle_fp_2src_half(s, opcode, rd, rn, rm);
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break;
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default:
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unallocated_encoding(s);
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}
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}
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/* Floating-point data-processing (3 source) - single precision */
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static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1,
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int rd, int rn, int rm, int ra)
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@ -7685,7 +7560,7 @@ static void disas_data_proc_fp(DisasContext *s, uint32_t insn)
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break;
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case 2:
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/* Floating point data-processing (2 source) */
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disas_fp_2src(s, insn);
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unallocated_encoding(s); /* in decodetree */
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break;
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case 3:
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/* Floating point conditional select */
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