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target/hppa: Fix hppa64 addressing 

In form_gva and cpu_get_tb_cpu_state, we must truncate when PSW_W == 0.
In space_select, the bits that choose the space depend on PSW_W.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-09-16 16:52:51 -07:00
parent 5718fe4cfe
commit 698240d19b
2 changed files with 16 additions and 13 deletions
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7
target/hppa/cpu.h
View File

@ -302,7 +302,7 @@ static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc,
#ifdef CONFIG_USER_ONLY
return off;
#else
off &= (psw & PSW_W ? 0x3fffffffffffffffull : 0xffffffffull);
off &= psw & PSW_W ? MAKE_64BIT_MASK(0, 62) : MAKE_64BIT_MASK(0, 32);
return spc | off;
#endif
}
@ -343,9 +343,8 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc,
flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P);
flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT;
*pc = (env->psw & PSW_C
? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4)
: env->iaoq_f & -4);
*pc = hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0),
env->iaoq_f & -4);
*cs_base = env->iasq_f;
/* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero

22
target/hppa/translate.c
View File

@ -710,6 +710,13 @@ static bool nullify_end(DisasContext *ctx)
return true;
}
static target_ureg gva_offset_mask(DisasContext *ctx)
{
return (ctx->tb_flags & PSW_W
? MAKE_64BIT_MASK(0, 62)
: MAKE_64BIT_MASK(0, 32));
}
static void copy_iaoq_entry(TCGv_reg dest, target_ureg ival, TCGv_reg vval)
{
if (unlikely(ival == -1)) {
@ -1398,7 +1405,8 @@ static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base)
tmp = tcg_temp_new();
spc = tcg_temp_new_tl();
tcg_gen_shri_reg(tmp, base, TARGET_REGISTER_BITS - 5);
/* Extract top 2 bits of the address, shift left 3 for uint64_t index. */
tcg_gen_shri_reg(tmp, base, (ctx->tb_flags & PSW_W ? 64 : 32) - 5);
tcg_gen_andi_reg(tmp, tmp, 030);
tcg_gen_trunc_reg_ptr(ptr, tmp);
@ -1415,6 +1423,7 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs,
{
TCGv_reg base = load_gpr(ctx, rb);
TCGv_reg ofs;
TCGv_tl addr;
/* Note that RX is mutually exclusive with DISP. */
if (rx) {
@ -1429,18 +1438,13 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs,
}
*pofs = ofs;
#ifdef CONFIG_USER_ONLY
*pgva = (modify <= 0 ? ofs : base);
#else
TCGv_tl addr = tcg_temp_new_tl();
*pgva = addr = tcg_temp_new_tl();
tcg_gen_extu_reg_tl(addr, modify <= 0 ? ofs : base);
if (ctx->tb_flags & PSW_W) {
tcg_gen_andi_tl(addr, addr, 0x3fffffffffffffffull);
}
tcg_gen_andi_tl(addr, addr, gva_offset_mask(ctx));
#ifndef CONFIG_USER_ONLY
if (!is_phys) {
tcg_gen_or_tl(addr, addr, space_select(ctx, sp, base));
}
*pgva = addr;
#endif
}