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riscv: Convert interrupt logs to use qemu_log_mask() 

Currently we log interrupts and exceptions using the trace backend in
riscv_cpu_do_interrupt(). We also log exceptions using the interrupt log
mask (-d int) in riscv_raise_exception().

This patch converts riscv_cpu_do_interrupt() to log both interrupts and
exceptions with the interrupt log mask, so that both are printed when a
user runs QEMU with -d int.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 29a8c766c7c4748d0f2711c3a0abb81208138c5e.1601652179.git.alistair.francis@wdc.com
This commit is contained in:
Alistair Francis 2020-10-02 08:24:14 -07:00
parent 4c5b97bfd0
commit 69430111ab
2 changed files with 7 additions and 2 deletions
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8
target/riscv/cpu_helper.c
View File

@ -895,7 +895,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
} }
trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, trace_riscv_trap(env->mhartid, async, cause, env->pc, tval,
riscv_cpu_get_trap_name(cause, async)); riscv_cpu_get_trap_name(cause, async));
qemu_log_mask(CPU_LOG_INT,
"%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", "
"epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n",
__func__, env->mhartid, async, cause, env->pc, tval,
riscv_cpu_get_trap_name(cause, async));
if (env->priv <= PRV_S && if (env->priv <= PRV_S &&
cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {

1
target/riscv/op_helper.c
View File

@ -29,7 +29,6 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
uint32_t exception, uintptr_t pc) uint32_t exception, uintptr_t pc)
{ {
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception);
cs->exception_index = exception; cs->exception_index = exception;
cpu_loop_exit_restore(cs, pc); cpu_loop_exit_restore(cs, pc);
} }