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hw/alpha: Drop latch_tmp hack 

The memory and i/o core now support passing 64-bit accesses along
from the guest, so we no longer need to emulate them.

Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2013-07-08 14:57:39 -07:00
parent 23326164ae
commit 678421650d
1 changed files with 12 additions and 41 deletions
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53
hw/alpha/typhoon.c
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@ -51,9 +51,6 @@ typedef struct TyphoonState {
TyphoonPchip pchip; TyphoonPchip pchip;
MemoryRegion dchip_region; MemoryRegion dchip_region;
MemoryRegion ram_region; MemoryRegion ram_region;
/* QEMU emulation state. */
uint32_t latch_tmp;
} TyphoonState; } TyphoonState;
/* Called when one of DRIR or DIM changes. */ /* Called when one of DRIR or DIM changes. */
@ -76,10 +73,6 @@ static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size)
TyphoonState *s = opaque; TyphoonState *s = opaque;
uint64_t ret = 0; uint64_t ret = 0;
if (addr & 4) {
return s->latch_tmp;
}
switch (addr) { switch (addr) {
case 0x0000: case 0x0000:
/* CSC: Cchip System Configuration Register. */ /* CSC: Cchip System Configuration Register. */
@ -199,7 +192,6 @@ static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size)
return -1; return -1;
} }
s->latch_tmp = ret >> 32;
return ret; return ret;
} }
@ -214,10 +206,6 @@ static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size)
TyphoonState *s = opaque; TyphoonState *s = opaque;
uint64_t ret = 0; uint64_t ret = 0;
if (addr & 4) {
return s->latch_tmp;
}
switch (addr) { switch (addr) {
case 0x0000: case 0x0000:
/* WSBA0: Window Space Base Address Register. */ /* WSBA0: Window Space Base Address Register. */
@ -302,23 +290,14 @@ static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size)
return -1; return -1;
} }
s->latch_tmp = ret >> 32;
return ret; return ret;
} }
static void cchip_write(void *opaque, hwaddr addr, static void cchip_write(void *opaque, hwaddr addr,
uint64_t v32, unsigned size) uint64_t val, unsigned size)
{ {
TyphoonState *s = opaque; TyphoonState *s = opaque;
uint64_t val, oldval, newval; uint64_t oldval, newval;
if (addr & 4) {
val = v32 << 32 | s->latch_tmp;
addr ^= 4;
} else {
s->latch_tmp = v32;
return;
}
switch (addr) { switch (addr) {
case 0x0000: case 0x0000:
@ -471,18 +450,10 @@ static void dchip_write(void *opaque, hwaddr addr,
} }
static void pchip_write(void *opaque, hwaddr addr, static void pchip_write(void *opaque, hwaddr addr,
uint64_t v32, unsigned size) uint64_t val, unsigned size)
{ {
TyphoonState *s = opaque; TyphoonState *s = opaque;
uint64_t val, oldval; uint64_t oldval;
if (addr & 4) {
val = v32 << 32 | s->latch_tmp;
addr ^= 4;
} else {
s->latch_tmp = v32;
return;
}
switch (addr) { switch (addr) {
case 0x0000: case 0x0000:
@ -585,12 +556,12 @@ static const MemoryRegionOps cchip_ops = {
.write = cchip_write, .write = cchip_write,
.endianness = DEVICE_LITTLE_ENDIAN, .endianness = DEVICE_LITTLE_ENDIAN,
.valid = { .valid = {
.min_access_size = 4, /* ??? Should be 8. */ .min_access_size = 8,
.max_access_size = 8, .max_access_size = 8,
}, },
.impl = { .impl = {
.min_access_size = 4, .min_access_size = 8,
.max_access_size = 4, .max_access_size = 8,
}, },
}; };
@ -599,11 +570,11 @@ static const MemoryRegionOps dchip_ops = {
.write = dchip_write, .write = dchip_write,
.endianness = DEVICE_LITTLE_ENDIAN, .endianness = DEVICE_LITTLE_ENDIAN,
.valid = { .valid = {
.min_access_size = 4, /* ??? Should be 8. */ .min_access_size = 8,
.max_access_size = 8, .max_access_size = 8,
}, },
.impl = { .impl = {
.min_access_size = 4, .min_access_size = 8,
.max_access_size = 8, .max_access_size = 8,
}, },
}; };
@ -613,12 +584,12 @@ static const MemoryRegionOps pchip_ops = {
.write = pchip_write, .write = pchip_write,
.endianness = DEVICE_LITTLE_ENDIAN, .endianness = DEVICE_LITTLE_ENDIAN,
.valid = { .valid = {
.min_access_size = 4, /* ??? Should be 8. */ .min_access_size = 8,
.max_access_size = 8, .max_access_size = 8,
}, },
.impl = { .impl = {
.min_access_size = 4, .min_access_size = 8,
.max_access_size = 4, .max_access_size = 8,
}, },
}; };