mirror of https://github.com/xemu-project/xemu.git
target/arm/tcg: refine cache descriptions with a wrapper
This patch allows for easier manipulation of the cache description register, CCSIDR. Which is helpful for testing as well. Currently, numbers get hard-coded and might be prone to errors. Therefore, this patch adds a wrapper for different types of CPUs available in tcg to decribe caches. One function `make_ccsidr` supports two cases by carrying a parameter as FORMAT that can be LEGACY and CCIDX which determines the specification of the register. For CCSIDR register, 32 bit version follows specification [1]. Conversely, 64 bit version follows specification [2]. [1] B4.1.19, ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition, https://developer.arm.com/documentation/ddi0406 [2] D23.2.29, ARM Architecture Reference Manual for A-profile Architecture, https://developer.arm.com/documentation/ddi0487/latest/ Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240903144550.280-1-alireza.sanaee@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Alireza Sanaee
Peter Maydell
parent
d54ffa54fb
commit
676624d757
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@ -21,6 +21,7 @@
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#define TARGET_ARM_FEATURES_H
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#include "hw/registerfields.h"
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#include "qemu/host-utils.h"
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/*
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* Naming convention for isar_feature functions:
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@ -1027,6 +1028,55 @@ static inline bool isar_feature_any_evt(const ARMISARegisters *id)
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return isar_feature_aa64_evt(id) || isar_feature_aa32_evt(id);
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}
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typedef enum {
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CCSIDR_FORMAT_LEGACY,
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CCSIDR_FORMAT_CCIDX,
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} CCSIDRFormat;
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static inline uint64_t make_ccsidr(CCSIDRFormat format, unsigned assoc,
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unsigned linesize, unsigned cachesize,
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uint8_t flags)
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{
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unsigned lg_linesize = ctz32(linesize);
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unsigned sets;
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uint64_t ccsidr = 0;
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assert(assoc != 0);
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assert(is_power_of_2(linesize));
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assert(lg_linesize >= 4 && lg_linesize <= 7 + 4);
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/* sets * associativity * linesize == cachesize. */
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sets = cachesize / (assoc * linesize);
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assert(cachesize % (assoc * linesize) == 0);
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if (format == CCSIDR_FORMAT_LEGACY) {
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/*
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* The 32-bit CCSIDR format is:
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* [27:13] number of sets - 1
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* [12:3] associativity - 1
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* [2:0] log2(linesize) - 4
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* so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
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*/
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ccsidr = deposit32(ccsidr, 28, 4, flags);
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ccsidr = deposit32(ccsidr, 13, 15, sets - 1);
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ccsidr = deposit32(ccsidr, 3, 10, assoc - 1);
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ccsidr = deposit32(ccsidr, 0, 3, lg_linesize - 4);
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} else {
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/*
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* The 64-bit CCSIDR_EL1 format is:
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* [55:32] number of sets - 1
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* [23:3] associativity - 1
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* [2:0] log2(linesize) - 4
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* so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
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*/
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ccsidr = deposit64(ccsidr, 32, 24, sets - 1);
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ccsidr = deposit64(ccsidr, 3, 21, assoc - 1);
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ccsidr = deposit64(ccsidr, 0, 3, lg_linesize - 4);
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}
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return ccsidr;
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}
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/*
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* Forward to the above feature tests given an ARMCPU pointer.
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*/
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@ -23,6 +23,7 @@
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#include "cpu.h"
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#include "cpregs.h"
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#include "qemu/module.h"
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#include "qemu/units.h"
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#include "sysemu/kvm.h"
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#include "sysemu/hvf.h"
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#include "sysemu/qtest.h"
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@ -642,9 +643,12 @@ static void aarch64_a57_initfn(Object *obj)
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cpu->isar.dbgdevid1 = 0x2;
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cpu->isar.reset_pmcr_el0 = 0x41013000;
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cpu->clidr = 0x0a200023;
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cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
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cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
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cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
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/* 32KB L1 dcache */
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cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7);
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/* 48KB L1 icache */
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cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2);
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/* 2048KB L2 cache */
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cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7);
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cpu->dcz_blocksize = 4; /* 64 bytes */
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cpu->gic_num_lrs = 4;
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cpu->gic_vpribits = 5;
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@ -700,9 +704,12 @@ static void aarch64_a53_initfn(Object *obj)
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cpu->isar.dbgdevid1 = 0x1;
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cpu->isar.reset_pmcr_el0 = 0x41033000;
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cpu->clidr = 0x0a200023;
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cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
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cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
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cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
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/* 32KB L1 dcache */
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cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7);
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/* 32KB L1 icache */
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cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 1, 64, 32 * KiB, 2);
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/* 1024KB L2 cache */
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cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 1 * MiB, 7);
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cpu->dcz_blocksize = 4; /* 64 bytes */
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cpu->gic_num_lrs = 4;
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cpu->gic_vpribits = 5;
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@ -29,32 +29,6 @@
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#include "cpu-features.h"
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#include "cpregs.h"
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static uint64_t make_ccsidr64(unsigned assoc, unsigned linesize,
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unsigned cachesize)
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{
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unsigned lg_linesize = ctz32(linesize);
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unsigned sets;
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/*
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* The 64-bit CCSIDR_EL1 format is:
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* [55:32] number of sets - 1
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* [23:3] associativity - 1
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* [2:0] log2(linesize) - 4
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* so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
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*/
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assert(assoc != 0);
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assert(is_power_of_2(linesize));
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assert(lg_linesize >= 4 && lg_linesize <= 7 + 4);
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/* sets * associativity * linesize == cachesize. */
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sets = cachesize / (assoc * linesize);
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assert(cachesize % (assoc * linesize) == 0);
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return ((uint64_t)(sets - 1) << 32)
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| ((assoc - 1) << 3)
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| (lg_linesize - 4);
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}
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static void aarch64_a35_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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@ -106,9 +80,12 @@ static void aarch64_a35_initfn(Object *obj)
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cpu->isar.reset_pmcr_el0 = 0x410a3000;
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/* From B2.29 Cache ID registers */
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cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
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cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
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cpu->ccsidr[2] = 0x703fe03a; /* 512KB L2 cache */
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/* 32KB L1 dcache */
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cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7);
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/* 32KB L1 icache */
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cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 2);
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/* 512KB L2 cache */
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cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 512 * KiB, 7);
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/* From B3.5 VGIC Type register */
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cpu->gic_num_lrs = 4;
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@ -272,9 +249,12 @@ static void aarch64_a55_initfn(Object *obj)
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cpu->revidr = 0;
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/* From B2.23 CCSIDR_EL1 */
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cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
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cpu->ccsidr[1] = 0x200fe01a; /* 32KB L1 icache */
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cpu->ccsidr[2] = 0x703fe07a; /* 512KB L2 cache */
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/* 32KB L1 dcache */
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cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7);
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/* 32KB L1 icache */
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cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 2);
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/* 512KB L2 cache */
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cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 512 * KiB, 7);
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/* From B2.96 SCTLR_EL3 */
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cpu->reset_sctlr = 0x30c50838;
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@ -338,9 +318,12 @@ static void aarch64_a72_initfn(Object *obj)
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cpu->isar.dbgdevid1 = 0x2;
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cpu->isar.reset_pmcr_el0 = 0x41023000;
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cpu->clidr = 0x0a200023;
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cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
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cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
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cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
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/* 32KB L1 dcache */
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cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7);
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/* 48KB L1 dcache */
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cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2);
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/* 1MB L2 cache */
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cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 1 * MiB, 7);
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cpu->dcz_blocksize = 4; /* 64 bytes */
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cpu->gic_num_lrs = 4;
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cpu->gic_vpribits = 5;
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@ -397,9 +380,12 @@ static void aarch64_a76_initfn(Object *obj)
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cpu->revidr = 0;
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/* From B2.18 CCSIDR_EL1 */
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cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
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cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
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cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
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/* 64KB L1 dcache */
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cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7);
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/* 64KB L1 icache */
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cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2);
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/* 512KB L2 cache */
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cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 512 * KiB, 7);
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/* From B2.93 SCTLR_EL3 */
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cpu->reset_sctlr = 0x30c50838;
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@ -449,9 +435,12 @@ static void aarch64_a64fx_initfn(Object *obj)
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cpu->isar.id_aa64isar1 = 0x0000000000010001;
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cpu->isar.id_aa64zfr0 = 0x0000000000000000;
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cpu->clidr = 0x0000000080000023;
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cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
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cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
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cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
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/* 64KB L1 dcache */
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cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB, 7);
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/* 64KB L1 icache */
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cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB, 2);
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/* 8MB L2 cache */
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cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 256, 8 * MiB, 7);
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cpu->dcz_blocksize = 6; /* 256 bytes */
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cpu->gic_num_lrs = 4;
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cpu->gic_vpribits = 5;
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@ -637,9 +626,12 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
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cpu->revidr = 0;
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/* From B2.23 CCSIDR_EL1 */
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cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
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cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
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cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
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/* 64KB L1 dcache */
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cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7);
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/* 64KB L1 icache */
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cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2);
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/* 1MB L2 dcache */
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cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 1 * MiB, 7);
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/* From B2.98 SCTLR_EL3 */
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cpu->reset_sctlr = 0x30c50838;
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@ -721,9 +713,12 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
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* L2: 8-way set associative, 64 byte line size, either 512K or 1MB.
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* L3: No L3 (this matches the CLIDR_EL1 value).
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*/
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cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */
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cpu->ccsidr[1] = cpu->ccsidr[0]; /* L1 icache */
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cpu->ccsidr[2] = make_ccsidr64(8, 64, 1 * MiB); /* L2 cache */
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/* 64KB L1 dcache */
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cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0);
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/* 64KB L1 icache */
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cpu->ccsidr[1] = cpu->ccsidr[0];
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/* 1MB L2 cache */
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cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 1 * MiB, 0);
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/* From 3.2.115 SCTLR_EL3 */
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cpu->reset_sctlr = 0x30c50838;
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@ -959,9 +954,12 @@ static void aarch64_a710_initfn(Object *obj)
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* L1: 4-way set associative 64-byte line size, total either 32K or 64K.
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* L2: 8-way set associative 64 byte line size, total either 256K or 512K.
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*/
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cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */
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cpu->ccsidr[1] = cpu->ccsidr[0]; /* L1 icache */
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cpu->ccsidr[2] = make_ccsidr64(8, 64, 512 * KiB); /* L2 cache */
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/* L1 dcache */
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cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0);
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/* L1 icache */
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cpu->ccsidr[1] = cpu->ccsidr[0];
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/* L2 cache */
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cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 512 * KiB, 0);
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/* FIXME: Not documented -- copied from neoverse-v1 */
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cpu->reset_sctlr = 0x30c50838;
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@ -1057,10 +1055,12 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
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* L1: 4-way set associative 64-byte line size, total 64K.
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* L2: 8-way set associative 64 byte line size, total either 512K or 1024K.
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*/
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cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */
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cpu->ccsidr[1] = cpu->ccsidr[0]; /* L1 icache */
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cpu->ccsidr[2] = make_ccsidr64(8, 64, 512 * KiB); /* L2 cache */
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/* L1 dcache */
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cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0);
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/* L1 icache */
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cpu->ccsidr[1] = cpu->ccsidr[0];
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/* L2 cache */
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cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 512 * KiB, 0);
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/* FIXME: Not documented -- copied from neoverse-v1 */
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cpu->reset_sctlr = 0x30c50838;
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