mirror of https://github.com/xemu-project/xemu.git
target/mips: Convert MSA FILL opcode to decodetree
Convert the FILL opcode (Vector Fill from GPR) to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-16-f4bug@amsat.org>
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@ -27,6 +27,7 @@
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@ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i
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@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
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@bz ...... ... df:2 wt:5 sa:16 &msa_bz
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@2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0
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@2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=0 df=%2r_df_w
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@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i
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@s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i
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@ -82,6 +83,7 @@ BNZ 010001 111 .. ..... ................ @bz
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SRARI 011110 010 ....... ..... ..... 001010 @bit
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SRLRI 011110 011 ....... ..... ..... 001010 @bit
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FILL 011110 11000000 .. ..... ..... 011110 @2r
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FCLASS 011110 110010000 . ..... ..... 011110 @2rf
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FTRUNC_S 011110 110010001 . ..... ..... 011110 @2rf
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FTRUNC_U 011110 110010010 . ..... ..... 011110 @2rf
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@ -61,7 +61,6 @@ enum {
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OPC_MSA_2R = (0x18 << 21) | OPC_MSA_VEC,
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/* 2R instruction df(bits 17..16) = _b, _h, _w, _d */
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OPC_FILL_df = (0x00 << 18) | OPC_MSA_2R,
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OPC_PCNT_df = (0x01 << 18) | OPC_MSA_2R,
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OPC_NLOC_df = (0x02 << 18) | OPC_MSA_2R,
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OPC_NLZC_df = (0x03 << 18) | OPC_MSA_2R,
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@ -1847,17 +1846,6 @@ static void gen_msa_2r(DisasContext *ctx)
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TCGv_i32 tws = tcg_const_i32(ws);
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switch (MASK_MSA_2R(ctx->opcode)) {
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case OPC_FILL_df:
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#if !defined(TARGET_MIPS64)
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/* Double format valid only for MIPS64 */
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if (df == DF_DOUBLE) {
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gen_reserved_instruction(ctx);
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break;
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}
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#endif
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gen_helper_msa_fill_df(cpu_env, tcg_constant_i32(df),
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twd, tws); /* trs */
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break;
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case OPC_NLOC_df:
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switch (df) {
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case DF_BYTE:
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@ -1916,6 +1904,25 @@ static void gen_msa_2r(DisasContext *ctx)
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tcg_temp_free_i32(tws);
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}
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static bool trans_FILL(DisasContext *ctx, arg_msa_r *a)
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{
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if (TARGET_LONG_BITS != 64 && a->df == DF_DOUBLE) {
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/* Double format valid only for MIPS64 */
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return false;
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}
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if (!check_msa_enabled(ctx)) {
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return true;
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}
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gen_helper_msa_fill_df(cpu_env,
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tcg_constant_i32(a->df),
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tcg_constant_i32(a->wd),
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tcg_constant_i32(a->ws));
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return true;
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}
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static bool trans_msa_2rf(DisasContext *ctx, arg_msa_r *a,
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gen_helper_piii *gen_msa_2rf)
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{
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