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trivial patches for 2024-02-22 

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Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging

trivial patches for 2024-02-22

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# gpg: Signature made Thu 22 Feb 2024 11:24:12 GMT
# gpg:                using RSA key 7B73BAD68BE7A2C289314B22701B4F6B1A693E59
# gpg:                issuer "mjt@tls.msk.ru"
# gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" [full]
# gpg:                 aka "Michael Tokarev <mjt@corpit.ru>" [full]
# gpg:                 aka "Michael Tokarev <mjt@debian.org>" [full]
# Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D  4324 457C E0A0 8044 65C5
#      Subkey fingerprint: 7B73 BAD6 8BE7 A2C2 8931  4B22 701B 4F6B 1A69 3E59

* tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu: (34 commits)
  system/vl: Update description for input grab key
  docs/system: Update description for input grab key
  hw/hppa/Kconfig: Fix building with "configure --without-default-devices"
  target/sparc: correct typos
  s390x: correct typos
  m68k: correct typos
  hexagon: correct typos
  ci/gitlab-pipeline-status: correct typos
  qemu-options.hx: correct typos
  qapi/ui: correct typos
  pc-bios/README: correct typos
  hw/riscv/virt.h: correct typos
  hw/net/npcm_gmac.h: correct typos
  hw/cxl/cxl_device.h: correct typos
  hw/arm/omap.h: correct typos
  include/exec/memory.h: correct typos
  sh4: correct typos
  ppc: correct typos
  loongson3: correct typos
  accel/tcg: correct typos
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2024-02-22 12:42:52 +00:00
parent 5cd3ae4903 185311130f
commit 6630bc04bc
46 changed files with 88 additions and 88 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
accel/tcg/ldst_atomicity.c.inc
View File

@ -76,7 +76,7 @@ static int required_atomicity(CPUState *cpu, uintptr_t p, MemOp memop)
/*
* Examine the alignment of p to determine if there are subobjects
* that must be aligned. Note that we only really need ctz4() --
* any more sigificant bits are discarded by the immediately
* any more significant bits are discarded by the immediately
* following comparison.
*/
tmp = ctz32(p);

2
docs/devel/ci-jobs.rst.inc
View File

@ -147,7 +147,7 @@ Set this variable to 1 to create the pipelines, but leave all
the jobs to be manually started from the UI
Set this variable to 2 to create the pipelines and run all
the jobs immediately, as was historicaly behaviour
the jobs immediately, as was the historical behaviour
QEMU_CI_AVOCADO_TESTING
~~~~~~~~~~~~~~~~~~~~~~~

2
docs/devel/docs.rst
View File

@ -21,7 +21,7 @@ are processed in two ways:
The syntax of these ``.hx`` files is simple. It is broadly an
alternation of C code put into the C output and rST format text
put into the documention. A few special directives are recognised;
put into the documentation. A few special directives are recognised;
these are all-caps and must be at the beginning of the line.
``HXCOMM`` is the comment marker. The line, including any arbitrary

2
docs/devel/testing.rst
View File

@ -728,7 +728,7 @@ For example to setup the HPPA ports builds of Debian::
EXECUTABLE=(pwd)/qemu-hppa V=1
The ``DEB_`` variables are substitutions used by
``debian-boostrap.pre`` which is called to do the initial debootstrap
``debian-bootstrap.pre`` which is called to do the initial debootstrap
of the rootfs before it is copied into the container. The second stage
is run as part of the build. The final image will be tagged as
``qemu/debian-sid-hppa``.

2
docs/interop/prl-xml.txt
View File

@ -122,7 +122,7 @@ Each Image element has following child elements:
* Type - image type of the element. It can be:
"Plain" for raw files.
"Compressed" for expanding disks.
* File - path to image file. Path can be relative to DiskDecriptor.xml or
* File - path to image file. Path can be relative to DiskDescriptor.xml or
absolute.
== Snapshots element ==

2
docs/interop/vhost-user.rst
View File

@ -989,7 +989,7 @@ When reconnecting:
#. If ``d.flags`` is not equal to the calculated flags value (means
back-end has submitted the buffer to guest driver before crash, so
it has to commit the in-progres update), set ``old_free_head``,
it has to commit the in-progress update), set ``old_free_head``,
``old_used_idx``, ``old_used_wrap_counter`` to ``free_head``,
``used_idx``, ``used_wrap_counter``

2
docs/system/devices/canokey.rst
View File

@ -14,7 +14,7 @@ CanoKey [1]_ is an open-source secure key with supports of
All these platform-independent features are in canokey-core [3]_.
For different platforms, CanoKey has different implementations,
including both hardware implementions and virtual cards:
including both hardware implementations and virtual cards:
* CanoKey STM32 [4]_
* CanoKey Pigeon [5]_

2
docs/system/keys.rst.inc
View File

@ -29,7 +29,7 @@ Ctrl-Alt-n
*3*
Serial port
Ctrl-Alt
Ctrl-Alt-g
Toggle mouse and keyboard grab.
In the virtual consoles, you can use Ctrl-Up, Ctrl-Down, Ctrl-PageUp and

4
hw/acpi/cpu_hotplug.c
View File

@ -13,8 +13,8 @@
#include "hw/acpi/cpu_hotplug.h"
#include "qapi/error.h"
#include "hw/core/cpu.h"
#include "hw/i386/pc.h"
#include "hw/pci/pci.h"
#include "hw/i386/x86.h"
#include "hw/pci/pci_device.h"
#include "qemu/error-report.h"
#define CPU_EJECT_METHOD "CPEJ"

2
hw/hppa/Kconfig
View File

@ -7,6 +7,7 @@ config HPPA_B160L
select DINO
select LASI
select SERIAL
select SERIAL_PCI
select ISA_BUS
select I8259
select IDE_CMD646
@ -16,3 +17,4 @@ config HPPA_B160L
select LASIPS2
select PARALLEL
select ARTIST
select USB_OHCI_PCI

1
hw/i386/acpi-common.c
View File

@ -27,7 +27,6 @@
#include "hw/acpi/acpi.h"
#include "hw/acpi/aml-build.h"
#include "hw/acpi/utils.h"
#include "hw/i386/pc.h"
#include "target/i386/cpu.h"
#include "acpi-build.h"

3
hw/i386/acpi-common.h
View File

@ -1,12 +1,15 @@
#ifndef HW_I386_ACPI_COMMON_H
#define HW_I386_ACPI_COMMON_H
#include "hw/boards.h"
#include "hw/acpi/bios-linker-loader.h"
#include "hw/i386/x86.h"
/* Default IOAPIC ID */
#define ACPI_BUILD_IOAPIC_ID 0x0
void pc_madt_cpu_entry(int uid, const CPUArchIdList *apic_ids,
GArray *entry, bool force_enabled);
void acpi_build_madt(GArray *table_data, BIOSLinker *linker,
X86MachineState *x86ms,
const char *oem_id, const char *oem_table_id);

2
hw/i386/kvm/ioapic.c
View File

@ -35,7 +35,7 @@ void kvm_pc_setup_irq_routing(bool pci_enabled)
kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_PIC_SLAVE, i - 8);
}
if (pci_enabled) {
for (i = 0; i < 24; ++i) {
for (i = 0; i < KVM_IOAPIC_NUM_PINS; ++i) {
if (i == 0) {
kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_IOAPIC, 2);
} else if (i != 2) {

1
hw/i386/port92.c
View File

@ -10,6 +10,7 @@
#include "sysemu/runstate.h"
#include "migration/vmstate.h"
#include "hw/irq.h"
#include "hw/isa/isa.h"
#include "hw/i386/pc.h"
#include "trace.h"
#include "qom/object.h"

1
hw/isa/lpc_ich9.c
View File

@ -41,7 +41,6 @@
#include "hw/isa/apm.h"
#include "hw/pci/pci.h"
#include "hw/southbridge/ich9.h"
#include "hw/i386/pc.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/ich9.h"
#include "hw/pci/pci_bus.h"

4
hw/mips/loongson3_bootp.h
View File

@ -25,7 +25,7 @@
struct efi_memory_map_loongson {
uint16_t vers; /* version of efi_memory_map */
uint32_t nr_map; /* number of memory_maps */
uint32_t mem_freq; /* memory frequence */
uint32_t mem_freq; /* memory frequency */
struct mem_map {
uint32_t node_id; /* node_id which memory attached to */
uint32_t mem_type; /* system memory, pci memory, pci io, etc. */
@ -156,7 +156,7 @@ struct board_devices {
struct loongson_special_attribute {
uint16_t vers; /* version of this special */
char special_name[64]; /* special_atribute_name */
char special_name[64]; /* special_attribute_name */
uint32_t loongson_special_type; /* type of special device */
/* for each device's resource */
struct resource_loongson resource[MAX_RESOURCE_NUMBER];

2
hw/sh4/sh7750_regs.h
View File

@ -172,7 +172,7 @@
/*
* Exeption-related registers
* Exception-related registers
*/
/* Immediate data for TRAPA instruction - TRA */

1
hw/timer/hpet.c
View File

@ -25,7 +25,6 @@
*/
#include "qemu/osdep.h"
#include "hw/i386/pc.h"
#include "hw/irq.h"
#include "qapi/error.h"
#include "qemu/error-report.h"

2
hw/usb/hcd-ehci-pci.c
View File

@ -83,7 +83,7 @@ static void usb_ehci_pci_init(Object *obj)
s->capsbase = 0x00;
s->opregbase = 0x20;
s->portscbase = 0x44;
s->portnr = NB_PORTS;
s->portnr = EHCI_PORTS;
if (!dc->hotpluggable) {
s->companion_enable = true;

2
hw/usb/hcd-ehci-sysbus.c
View File

@ -88,7 +88,7 @@ static void ehci_sysbus_class_init(ObjectClass *klass, void *data)
SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(klass);
sec->portscbase = 0x44;
sec->portnr = NB_PORTS;
sec->portnr = EHCI_PORTS;
dc->realize = usb_ehci_sysbus_realize;
dc->vmsd = &vmstate_ehci_sysbus;

21
hw/usb/hcd-ehci.c
View File

@ -783,9 +783,9 @@ static void ehci_register_companion(USBBus *bus, USBPort *ports[],
EHCIState *s = container_of(bus, EHCIState, bus);
uint32_t i;
if (firstport + portcount > NB_PORTS) {
if (firstport + portcount > EHCI_PORTS) {
error_setg(errp, "firstport must be between 0 and %u",
NB_PORTS - portcount);
EHCI_PORTS - portcount);
return;
}
@ -831,7 +831,7 @@ static USBDevice *ehci_find_device(EHCIState *ehci, uint8_t addr)
USBPort *port;
int i;
for (i = 0; i < NB_PORTS; i++) {
for (i = 0; i < EHCI_PORTS; i++) {
port = &ehci->ports[i];
if (!(ehci->portsc[i] & PORTSC_PED)) {
DPRINTF("Port %d not enabled\n", i);
@ -850,7 +850,7 @@ void ehci_reset(void *opaque)
{
EHCIState *s = opaque;
int i;
USBDevice *devs[NB_PORTS];
USBDevice *devs[EHCI_PORTS];
trace_usb_ehci_reset();
@ -858,7 +858,7 @@ void ehci_reset(void *opaque)
* Do the detach before touching portsc, so that it correctly gets send to
* us or to our companion based on PORTSC_POWNER before the reset.
*/
for(i = 0; i < NB_PORTS; i++) {
for(i = 0; i < EHCI_PORTS; i++) {
devs[i] = s->ports[i].dev;
if (devs[i] && devs[i]->attached) {
usb_detach(&s->ports[i]);
@ -877,7 +877,7 @@ void ehci_reset(void *opaque)
s->astate = EST_INACTIVE;
s->pstate = EST_INACTIVE;
for(i = 0; i < NB_PORTS; i++) {
for(i = 0; i < EHCI_PORTS; i++) {
if (s->companion_ports[i]) {
s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
} else {
@ -1086,8 +1086,9 @@ static void ehci_opreg_write(void *ptr, hwaddr addr,
case CONFIGFLAG:
val &= 0x1;
if (val) {
for(i = 0; i < NB_PORTS; i++)
for (i = 0; i < EHCI_PORTS; i++) {
handle_port_owner_write(s, i, 0);
}
}
break;
@ -2426,7 +2427,7 @@ static int usb_ehci_post_load(void *opaque, int version_id)
EHCIState *s = opaque;
int i;
for (i = 0; i < NB_PORTS; i++) {
for (i = 0; i < EHCI_PORTS; i++) {
USBPort *companion = s->companion_ports[i];
if (companion == NULL) {
continue;
@ -2508,9 +2509,9 @@ void usb_ehci_realize(EHCIState *s, DeviceState *dev, Error **errp)
{
int i;
if (s->portnr > NB_PORTS) {
if (s->portnr > EHCI_PORTS) {
error_setg(errp, "Too many ports! Max. port number is %d.",
NB_PORTS);
EHCI_PORTS);
return;
}
if (s->maxframes < 8 || s->maxframes > 512) {

8
hw/usb/hcd-ehci.h
View File

@ -37,7 +37,7 @@
#define MMIO_SIZE 0x1000
#define CAPA_SIZE 0x10
#define NB_PORTS 6 /* Max. Number of downstream ports */
#define EHCI_PORTS 6 /* Max. Number of downstream ports */
typedef struct EHCIPacket EHCIPacket;
typedef struct EHCIQueue EHCIQueue;
@ -288,7 +288,7 @@ struct EHCIState {
uint32_t configflag;
};
};
uint32_t portsc[NB_PORTS];
uint32_t portsc[EHCI_PORTS];
/*
* Internal states, shadow registers, etc
@ -298,8 +298,8 @@ struct EHCIState {
bool working;
uint32_t astate; /* Current state in asynchronous schedule */
uint32_t pstate; /* Current state in periodic schedule */
USBPort ports[NB_PORTS];
USBPort *companion_ports[NB_PORTS];
USBPort ports[EHCI_PORTS];
USBPort *companion_ports[EHCI_PORTS];
uint32_t usbsts_pending;
uint32_t usbsts_frindex;
EHCIQueueHead aqueues;

24
hw/usb/hcd-uhci.c
View File

@ -322,7 +322,7 @@ static void uhci_reset(DeviceState *dev)
s->fl_base_addr = 0;
s->sof_timing = 64;
for(i = 0; i < NB_PORTS; i++) {
for(i = 0; i < UHCI_PORTS; i++) {
port = &s->ports[i];
port->ctrl = 0x0080;
if (port->port.dev && port->port.dev->attached) {
@ -364,7 +364,7 @@ static const VMStateDescription vmstate_uhci = {
.fields = (const VMStateField[]) {
VMSTATE_PCI_DEVICE(dev, UHCIState),
VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState, NULL),
VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1,
VMSTATE_STRUCT_ARRAY(ports, UHCIState, UHCI_PORTS, 1,
vmstate_uhci_port, UHCIPort),
VMSTATE_UINT16(cmd, UHCIState),
VMSTATE_UINT16(status, UHCIState),
@ -404,7 +404,7 @@ static void uhci_port_write(void *opaque, hwaddr addr,
int i;
/* send reset on the USB bus */
for(i = 0; i < NB_PORTS; i++) {
for(i = 0; i < UHCI_PORTS; i++) {
port = &s->ports[i];
usb_device_reset(port->port.dev);
}
@ -457,8 +457,9 @@ static void uhci_port_write(void *opaque, hwaddr addr,
int n;
n = (addr >> 1) & 7;
if (n >= NB_PORTS)
if (n >= UHCI_PORTS) {
return;
}
port = &s->ports[n];
dev = port->port.dev;
if (dev && dev->attached) {
@ -513,8 +514,9 @@ static uint64_t uhci_port_read(void *opaque, hwaddr addr, unsigned size)
UHCIPort *port;
int n;
n = (addr >> 1) & 7;
if (n >= NB_PORTS)
if (n >= UHCI_PORTS) {
goto read_default;
}
port = &s->ports[n];
val = port->ctrl;
}
@ -607,7 +609,7 @@ static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr)
USBDevice *dev;
int i;
for (i = 0; i < NB_PORTS; i++) {
for (i = 0; i < UHCI_PORTS; i++) {
UHCIPort *port = &s->ports[i];
if (!(port->ctrl & UHCI_PORT_EN)) {
continue;
@ -1171,11 +1173,11 @@ void usb_uhci_common_realize(PCIDevice *dev, Error **errp)
s->irq = pci_allocate_irq(dev);
if (s->masterbus) {
USBPort *ports[NB_PORTS];
for(i = 0; i < NB_PORTS; i++) {
USBPort *ports[UHCI_PORTS];
for(i = 0; i < UHCI_PORTS; i++) {
ports[i] = &s->ports[i].port;
}
usb_register_companion(s->masterbus, ports, NB_PORTS,
usb_register_companion(s->masterbus, ports, UHCI_PORTS,
s->firstport, s, &uhci_port_ops,
USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL,
&err);
@ -1185,14 +1187,14 @@ void usb_uhci_common_realize(PCIDevice *dev, Error **errp)
}
} else {
usb_bus_new(&s->bus, sizeof(s->bus), &uhci_bus_ops, DEVICE(dev));
for (i = 0; i < NB_PORTS; i++) {
for (i = 0; i < UHCI_PORTS; i++) {
usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops,
USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
}
}
s->bh = qemu_bh_new_guarded(uhci_bh, s, &DEVICE(dev)->mem_reentrancy_guard);
s->frame_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, uhci_frame_timer, s);
s->num_ports_vmstate = NB_PORTS;
s->num_ports_vmstate = UHCI_PORTS;
QTAILQ_INIT(&s->queues);
memory_region_init_io(&s->io_bar, OBJECT(s), &uhci_ioport_ops, s,

4
hw/usb/hcd-uhci.h
View File

@ -35,7 +35,7 @@
typedef struct UHCIQueue UHCIQueue;
#define NB_PORTS 2
#define UHCI_PORTS 2
typedef struct UHCIPort {
USBPort port;
@ -59,7 +59,7 @@ typedef struct UHCIState {
uint32_t frame_bytes;
uint32_t frame_bandwidth;
bool completions_only;
UHCIPort ports[NB_PORTS];
UHCIPort ports[UHCI_PORTS];
qemu_irq irq;
/* Interrupts that should be raised at the end of the current frame. */
uint32_t pending_int_mask;

2
include/exec/memory.h
View File

@ -3146,7 +3146,7 @@ int ram_block_discard_require(bool state);
/*
* See ram_block_discard_require(): only inhibit technologies that disable
* uncoordinated discarding of pages in RAM blocks, allowing co-existance with
* uncoordinated discarding of pages in RAM blocks, allowing co-existence with
* technologies that only inhibit uncoordinated discards (via the
* RamDiscardManager).
*/

3
include/hw/arm/omap.h
View File

@ -1008,7 +1008,8 @@ void omap_mpu_wakeup(void *opaque, int irq, int req);
__func__, paddr)
/* OMAP-specific Linux bootloader tags for the ATAG_BOARD area
(Board-specifc tags are not here) */
* (Board-specific tags are not here)
*/
#define OMAP_TAG_CLOCK 0x4f01
#define OMAP_TAG_MMC 0x4f02
#define OMAP_TAG_SERIAL_CONSOLE 0x4f03

4
include/hw/cxl/cxl_device.h
View File

@ -268,7 +268,7 @@ void cxl_event_set_status(CXLDeviceState *cxl_dstate, CXLEventLogType log_type,
/*
* Helper macro to initialize capability headers for CXL devices.
*
* In CXL r3.1 Section 8.2.8.2: CXL Device Capablity Header Register, this is
* In CXL r3.1 Section 8.2.8.2: CXL Device Capability Header Register, this is
* listed as a 128b register, but in CXL r3.1 Section 8.2.8: CXL Device Register
* Interface, it says:
* > No registers defined in Section 8.2.8 are larger than 64-bits wide so that
@ -276,7 +276,7 @@ void cxl_event_set_status(CXLDeviceState *cxl_dstate, CXLEventLogType log_type,
* > followed, the behavior is undefined.
*
* > To illustrate how the fields fit together, the layouts ... are shown as
* > wider than a 64 bit register. Implemenations are expected to use any size
* > wider than a 64 bit register. Implementations are expected to use any size
* > accesses for this information up to 64 bits without lost of functionality
*
* Here we've chosen to make it 4 dwords.

6
include/hw/i386/pc.h
View File

@ -15,8 +15,6 @@
#include "hw/firmware/smbios.h"
#include "hw/cxl/cxl.h"
#define HPET_INTCAP "hpet-intcap"
/**
* PCMachineState:
* @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling
@ -201,10 +199,6 @@ bool pc_system_ovmf_table_find(const char *entry, uint8_t **data,
int *data_len);
void pc_system_parse_ovmf_flash(uint8_t *flash_ptr, size_t flash_size);
/* hw/i386/acpi-common.c */
void pc_madt_cpu_entry(int uid, const CPUArchIdList *apic_ids,
GArray *entry, bool force_enabled);
/* sgx.c */
void pc_machine_init_sgx_epc(PCMachineState *pcms);

4
include/hw/net/npcm_gmac.h
View File

@ -81,7 +81,7 @@ struct NPCMGMACRxDesc {
/* Disable Interrupt on Completion */
#define RX_DESC_RDES1_DIS_INTR_COMP_MASK BIT(31)
/* Recieve end of ring */
/* Receive end of ring */
#define RX_DESC_RDES1_RC_END_RING_MASK BIT(25)
/* Second Address Chained */
#define RX_DESC_RDES1_SEC_ADDR_CHND_MASK BIT(24)
@ -213,7 +213,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(NPCMGMACState, NPCM_GMAC)
#define NPCM_DMA_STATUS_FBI BIT(13)
/* Early transmit Interrupt */
#define NPCM_DMA_STATUS_ETI BIT(10)
/* Receive Watchdog Timout */
/* Receive Watchdog Timeout */
#define NPCM_DMA_STATUS_RWT BIT(9)
/* Receive Process Stopped */
#define NPCM_DMA_STATUS_RPS BIT(8)

4
include/hw/riscv/virt.h
View File

@ -144,13 +144,13 @@ uint32_t imsic_num_bits(uint32_t count);
#define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
#if VIRT_IMSIC_GROUP_MAX_SIZE < \
IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
#error "Can't accomodate single IMSIC group in address space"
#error "Can't accommodate single IMSIC group in address space"
#endif
#define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \
VIRT_IMSIC_GROUP_MAX_SIZE)
#if 0x4000000 < VIRT_IMSIC_MAX_SIZE
#error "Can't accomodate all IMSIC groups in address space"
#error "Can't accommodate all IMSIC groups in address space"
#endif
#endif

2
include/hw/timer/hpet.h
View File

@ -78,6 +78,8 @@ extern struct hpet_fw_config hpet_cfg;
#define TYPE_HPET "hpet"
#define HPET_INTCAP "hpet-intcap"
static inline bool hpet_find(void)
{
return object_resolve_path_type("", TYPE_HPET, NULL);

2
pc-bios/README
View File

@ -67,7 +67,7 @@
and enable the use of well-known bootloaders such as U-Boot.
OpenSBI is distributed under the terms of the BSD 2-clause license
("Simplified BSD License" or "FreeBSD License", SPDX: BSD-2-Clause). OpenSBI
source code also contains code reused from other projects desribed here:
source code also contains code reused from other projects described here:
https://github.com/riscv/opensbi/blob/master/ThirdPartyNotices.md.
- npcm7xx_bootrom.bin is a simplified, free (Apache 2.0) boot ROM for Nuvoton

4
qapi/ui.json
View File

@ -63,7 +63,7 @@
##
# @SetPasswordOptionsVnc:
#
# Options for set_password specific to the VNC procotol.
# Options for set_password specific to the VNC protocol.
#
# @display: The id of the display where the password should be
# changed. Defaults to the first.
@ -125,7 +125,7 @@
##
# @ExpirePasswordOptionsVnc:
#
# Options for expire_password specific to the VNC procotol.
# Options for expire_password specific to the VNC protocol.
#
# @display: The id of the display where the expiration should be
# changed. Defaults to the first.

4
qemu-options.hx
View File

@ -2468,7 +2468,7 @@ SRST
``to=L``
With this option, QEMU will try next available VNC displays,
until the number L, if the origianlly defined "-vnc display" is
until the number L, if the originally defined "-vnc display" is
not available, e.g. port 5900+display is already used by another
application. By default, to=0.
@ -5511,7 +5511,7 @@ SRST
-object filter-redirector,netdev=hn0,id=redire0,queue=rx,indev=compare_out
-object filter-redirector,netdev=hn0,id=redire1,queue=rx,outdev=compare0
-object iothread,id=iothread1
-object colo-compare,id=comp0,primary_in=compare0-0,secondary_in=compare1,outdev=compare_out0,notify_dev=nofity_way,iothread=iothread1
-object colo-compare,id=comp0,primary_in=compare0-0,secondary_in=compare1,outdev=compare_out0,notify_dev=notify_way,iothread=iothread1
secondary:
-netdev tap,id=hn0,vhost=off

2
scripts/ci/gitlab-pipeline-status
View File

@ -131,7 +131,7 @@ def create_parser():
'checks of the pipeline status. Defaults '
'to %(default)s'))
parser.add_argument('-w', '--wait', action='store_true', default=False,
help=('Wether to wait, instead of checking only once '
help=('Whether to wait, instead of checking only once '
'the status of a pipeline'))
parser.add_argument('-p', '--project-id', type=int, default=11167699,
help=('The GitLab project ID. Defaults to the project '

7
system/physmem.c
View File

@ -2154,10 +2154,8 @@ void qemu_ram_remap(ram_addr_t addr, ram_addr_t length)
*
* Called within RCU critical section.
*/
void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr)
void *qemu_map_ram_ptr(RAMBlock *block, ram_addr_t addr)
{
RAMBlock *block = ram_block;
if (block == NULL) {
block = qemu_get_ram_block(addr);
addr -= block->offset;
@ -2182,10 +2180,9 @@ void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr)
*
* Called within RCU critical section.
*/
static void *qemu_ram_ptr_length(RAMBlock *ram_block, ram_addr_t addr,
static void *qemu_ram_ptr_length(RAMBlock *block, ram_addr_t addr,
hwaddr *size, bool lock)
{
RAMBlock *block = ram_block;
if (*size == 0) {
return NULL;
}

2
system/vl.c
View File

@ -891,7 +891,7 @@ static void help(int exitcode)
printf("\nDuring emulation, the following keys are useful:\n"
"ctrl-alt-f toggle full screen\n"
"ctrl-alt-n switch to virtual console 'n'\n"
"ctrl-alt toggle mouse and keyboard grab\n"
"ctrl-alt-g toggle mouse and keyboard grab\n"
"\n"
"When using -nographic, press 'ctrl-a h' to get some help.\n"
"\n"

2
target/hexagon/idef-parser/macros.inc
View File

@ -127,5 +127,5 @@
/* Include fHIDE macros which hide type declarations */
#define fHIDE(A) A
/* Purge non-relavant parts */
/* Purge non-relevant parts */
#define fBRANCH_SPECULATE_STALL(A, B, C, D, E)

1
target/i386/monitor.c
View File

@ -33,7 +33,6 @@
#include "qapi/error.h"
#include "qapi/qapi-commands-misc-target.h"
#include "qapi/qapi-commands-misc.h"
#include "hw/i386/pc.h"
/* Perform linear address sign extension */
static hwaddr addr_canonical(CPUArchState *env, hwaddr addr)

7
target/m68k/cpu.h
View File

@ -478,10 +478,11 @@ void do_m68k_semihosting(CPUM68KState *env, int nr);
* The 68000 family is defined in six main CPU classes, the 680[012346]0.
* Generally each successive CPU adds enhanced data/stack/instructions.
* However, some features are only common to one, or a few classes.
* The features covers those subsets of instructons.
* The features cover those subsets of instructions.
*
* CPU32/32+ are basically 680010 compatible with some 68020 class instructons,
* and some additional CPU32 instructions. Mostly Supervisor state differences.
* CPU32/32+ are basically 680010 compatible with some 68020 class
* instructions, and some additional CPU32 instructions. Mostly Supervisor
* state differences.
*
* The ColdFire core ISA is a RISC-style reduction of the 68000 series cpu.
* There are 4 ColdFire core ISA revisions: A, A+, B and C.

2
target/ppc/translate/vmx-impl.c.inc
View File

@ -1183,7 +1183,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
/*
* Support for Altivec instructions that use bit 31 (Rc) as an opcode
* bit but also use bit 21 as an actual Rc bit. In general, thse pairs
* bit but also use bit 21 as an actual Rc bit. In general, these pairs
* come from different versions of the ISA, so we must also support a
* pair of flags for each instruction.
*/

2
target/s390x/cpu_features_def.h.inc
View File

@ -142,7 +142,7 @@ DEF_FEAT(SIE_CEI, "cei", SCLP_CPU, 43, "SIE: Conditional-external-interception f
/*
* Features exposed via no feature bit (but e.g., instruction sensing)
* -> the feature bit number is irrelavant
* -> the feature bit number is irrelevant
*/
DEF_FEAT(DAT_ENH_2, "dateh2", MISC, 0, "DAT-enhancement facility 2")
DEF_FEAT(CMM, "cmm", MISC, 0, "Collaborative-memory-management facility")

8
target/sparc/asi.h
View File

@ -145,14 +145,14 @@
* and later ASIs.
*/
#define ASI_REAL 0x14 /* Real address, cacheable */
#define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cachable */
#define ASI_REAL_IO 0x15 /* Real address, non-cachable */
#define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cacheable */
#define ASI_REAL_IO 0x15 /* Real address, non-cacheable */
#define ASI_PHYS_BYPASS_EC_E 0x15 /* PADDR, E-bit */
#define ASI_BLK_AIUP_4V 0x16 /* (4V) Prim, user, block ld/st */
#define ASI_BLK_AIUS_4V 0x17 /* (4V) Sec, user, block ld/st */
#define ASI_REAL_L 0x1c /* Real address, cacheable, LE */
#define ASI_PHYS_USE_EC_L 0x1c /* PADDR, E-cachable, little endian*/
#define ASI_REAL_IO_L 0x1d /* Real address, non-cachable, LE */
#define ASI_PHYS_USE_EC_L 0x1c /* PADDR, E-cacheable, little endian*/
#define ASI_REAL_IO_L 0x1d /* Real address, non-cacheable, LE */
#define ASI_PHYS_BYPASS_EC_E_L 0x1d /* PADDR, E-bit, little endian */
#define ASI_BLK_AIUP_L_4V 0x1e /* (4V) Prim, user, block, l-endian*/
#define ASI_BLK_AIUS_L_4V 0x1f /* (4V) Sec, user, block, l-endian */

2
tests/avocado/acpi-bits/bits-tests/smbios.py2
View File

@ -1060,7 +1060,7 @@ class EventLogDescriptor(unpack.Struct):
0x16: 'Log Area Reset/Cleared',
0x17: 'System boot',
xrange(0x18, 0x7F): 'Unused, available for assignment',
xrange(0x80, 0xFE): 'Availalbe for system- and OEM-specific assignments',
xrange(0x80, 0xFE): 'Available for system- and OEM-specific assignments',
0xFF: 'End of log'
}
yield 'log_type', u.unpack_one('B'), unpack.format_table("{}", _event_log_type_descriptors)

6
tests/avocado/mem-addr-space-check.py
View File

@ -165,7 +165,7 @@ class MemAddrCheck(QemuSystemTest):
For q35-7.0 machines, "above 4G" memory starts are 4G.
pci64_hole size is 32 GiB. Since TCG_PHYS_ADDR_BITS is defined to
be 40, TCG emulated CPUs have maximum of 1 TiB (1024 GiB) of
directly addressible memory.
directly addressable memory.
Hence, maxmem value at most can be
1024 GiB - 4 GiB - 1 GiB per slot for alignment - 32 GiB + 0.5 GiB
which is equal to 987.5 GiB. Setting the value to 988 GiB should
@ -190,7 +190,7 @@ class MemAddrCheck(QemuSystemTest):
AMD_HT_START is defined to be at 1012 GiB. So for q35 machines
version > 7.0 and AMD cpus, instead of 1024 GiB limit for 40 bit
processor address space, it has to be 1012 GiB , that is 12 GiB
less than the case above in order to accomodate HT hole.
less than the case above in order to accommodate HT hole.
Make sure QEMU fails when maxmem size is 976 GiB (12 GiB less
than 988 GiB).
"""
@ -297,7 +297,7 @@ class MemAddrCheck(QemuSystemTest):
:avocado: tags=arch:x86_64
AMD processor with 41 bits. Max cpu hw address = 2 TiB.
Same as above but by setting maxram beween 976 GiB and 992 Gib,
Same as above but by setting maxram between 976 GiB and 992 Gib,
QEMU should start fine.
"""
self.vm.add_args('-S', '-cpu', 'EPYC-v4,phys-bits=41',

2
tests/avocado/reverse_debugging.py
View File

@ -191,7 +191,7 @@ class ReverseDebugging(LinuxKernelTest):
self.check_pc(g, steps[-1])
logger.info('successfully reached %x' % steps[-1])
logger.info('exitting gdb and qemu')
logger.info('exiting gdb and qemu')
vm.shutdown()
class ReverseDebugging_X86_64(ReverseDebugging):