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mcf5206: convert to memory API 

Signed-off-by: Benoît Canet <benoit.canet@gmail.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Benoît Canet 2011-11-24 14:31:12 +01:00 committed by Avi Kivity
parent 9244b42dea
commit 653fa85c9a
3 changed files with 26 additions and 18 deletions
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2
hw/an5206.c
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@ -53,7 +53,7 @@ static void an5206_init(ram_addr_t ram_size,
memory_region_init_ram(sram, NULL, "an5206.sram", 512); memory_region_init_ram(sram, NULL, "an5206.sram", 512);
memory_region_add_subregion(address_space_mem, AN5206_RAMBAR_ADDR, sram); memory_region_add_subregion(address_space_mem, AN5206_RAMBAR_ADDR, sram);
mcf5206_init(AN5206_MBAR_ADDR, env); mcf5206_init(address_space_mem, AN5206_MBAR_ADDR, env);
/* Load kernel. */ /* Load kernel. */
if (!kernel_filename) { if (!kernel_filename) {

5
hw/mcf.h
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@ -2,6 +2,8 @@
#define HW_MCF_H #define HW_MCF_H
/* Motorola ColdFire device prototypes. */ /* Motorola ColdFire device prototypes. */
struct MemoryRegion;
/* mcf_uart.c */ /* mcf_uart.c */
uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr); uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val); void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val);
@ -16,6 +18,7 @@ qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq); void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
/* mcf5206.c */ /* mcf5206.c */
qemu_irq *mcf5206_init(uint32_t base, CPUState *env); qemu_irq *mcf5206_init(struct MemoryRegion *sysmem,
uint32_t base, CPUState *env);
#endif #endif

29
hw/mcf5206.c
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@ -9,6 +9,7 @@
#include "mcf.h" #include "mcf.h"
#include "qemu-timer.h" #include "qemu-timer.h"
#include "sysemu.h" #include "sysemu.h"
#include "exec-memory.h"
/* General purpose timer module. */ /* General purpose timer module. */
typedef struct { typedef struct {
@ -144,6 +145,7 @@ static m5206_timer_state *m5206_timer_init(qemu_irq irq)
typedef struct { typedef struct {
CPUState *env; CPUState *env;
MemoryRegion iomem;
m5206_timer_state *timer[2]; m5206_timer_state *timer[2];
void *uart[2]; void *uart[2];
uint8_t scr; uint8_t scr;
@ -505,29 +507,32 @@ static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset,
m5206_mbar_write(s, offset, value); m5206_mbar_write(s, offset, value);
} }
static CPUReadMemoryFunc * const m5206_mbar_readfn[] = { static const MemoryRegionOps m5206_mbar_ops = {
.old_mmio = {
.read = {
m5206_mbar_readb, m5206_mbar_readb,
m5206_mbar_readw, m5206_mbar_readw,
m5206_mbar_readl m5206_mbar_readl,
}; },
.write = {
static CPUWriteMemoryFunc * const m5206_mbar_writefn[] = {
m5206_mbar_writeb, m5206_mbar_writeb,
m5206_mbar_writew, m5206_mbar_writew,
m5206_mbar_writel m5206_mbar_writel,
},
},
.endianness = DEVICE_NATIVE_ENDIAN,
}; };
qemu_irq *mcf5206_init(uint32_t base, CPUState *env) qemu_irq *mcf5206_init(MemoryRegion *sysmem, uint32_t base, CPUState *env)
{ {
m5206_mbar_state *s; m5206_mbar_state *s;
qemu_irq *pic; qemu_irq *pic;
int iomemtype;
s = (m5206_mbar_state *)g_malloc0(sizeof(m5206_mbar_state)); s = (m5206_mbar_state *)g_malloc0(sizeof(m5206_mbar_state));
iomemtype = cpu_register_io_memory(m5206_mbar_readfn,
m5206_mbar_writefn, s, memory_region_init_io(&s->iomem, &m5206_mbar_ops, s,
DEVICE_NATIVE_ENDIAN); "mbar", 0x00001000);
cpu_register_physical_memory(base, 0x00001000, iomemtype); memory_region_add_subregion(sysmem, base, &s->iomem);
pic = qemu_allocate_irqs(m5206_mbar_set_irq, s, 14); pic = qemu_allocate_irqs(m5206_mbar_set_irq, s, 14);
s->timer[0] = m5206_timer_init(pic[9]); s->timer[0] = m5206_timer_init(pic[9]);