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target/mips: Add emulation of misc nanoMIPS instructions (pool32axf)
Add emulation of misc nanoMIPS instructions situated in pool32axf. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
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@ -17034,6 +17034,89 @@ static void gen_pool32a0_nanomips_insn(DisasContext *ctx)
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}
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}
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static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
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{
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#ifndef CONFIG_USER_ONLY
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int rt = extract32(ctx->opcode, 21, 5);
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int rs = extract32(ctx->opcode, 16, 5);
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#endif
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switch (extract32(ctx->opcode, 6, 3)) {
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case NM_POOL32AXF_4:
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case NM_POOL32AXF_5:
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switch (extract32(ctx->opcode, 9, 7)) {
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#ifndef CONFIG_USER_ONLY
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case NM_TLBP:
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gen_cp0(env, ctx, OPC_TLBP, 0, 0);
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break;
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case NM_TLBR:
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gen_cp0(env, ctx, OPC_TLBR, 0, 0);
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break;
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case NM_TLBWI:
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gen_cp0(env, ctx, OPC_TLBWI, 0, 0);
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break;
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case NM_TLBWR:
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gen_cp0(env, ctx, OPC_TLBWR, 0, 0);
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break;
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case NM_TLBINV:
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gen_cp0(env, ctx, OPC_TLBINV, 0, 0);
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break;
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case NM_TLBINVF:
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gen_cp0(env, ctx, OPC_TLBINVF, 0, 0);
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break;
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case NM_DI:
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check_cp0_enabled(ctx);
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{
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TCGv t0 = tcg_temp_new();
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save_cpu_state(ctx, 1);
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gen_helper_di(t0, cpu_env);
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gen_store_gpr(t0, rt);
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/* Stop translation as we may have switched the execution mode */
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ctx->base.is_jmp = DISAS_STOP;
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tcg_temp_free(t0);
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}
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break;
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case NM_EI:
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check_cp0_enabled(ctx);
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{
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TCGv t0 = tcg_temp_new();
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save_cpu_state(ctx, 1);
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gen_helper_ei(t0, cpu_env);
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gen_store_gpr(t0, rt);
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/* Stop translation as we may have switched the execution mode */
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ctx->base.is_jmp = DISAS_STOP;
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tcg_temp_free(t0);
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}
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break;
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case NM_RDPGPR:
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gen_load_srsgpr(rs, rt);
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break;
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case NM_WRPGPR:
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gen_store_srsgpr(rs, rt);
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break;
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case NM_WAIT:
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gen_cp0(env, ctx, OPC_WAIT, 0, 0);
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break;
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case NM_DERET:
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gen_cp0(env, ctx, OPC_DERET, 0, 0);
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break;
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case NM_ERETX:
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gen_cp0(env, ctx, OPC_ERET, 0, 0);
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break;
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#endif
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default:
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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break;
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default:
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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}
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static void gen_pool32f_nanomips_insn(DisasContext *ctx)
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{
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int rt, rs, rd;
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@ -17404,6 +17487,14 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
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gen_pool32a0_nanomips_insn(ctx);
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break;
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case NM_POOL32A7:
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switch (extract32(ctx->opcode, 3, 3)) {
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case NM_POOL32AXF:
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gen_pool32axf_nanomips_insn(env, ctx);
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break;
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default:
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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break;
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default:
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generate_exception_end(ctx, EXCP_RI);
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