mirror of https://github.com/xemu-project/xemu.git
hw/intc/arm_gicv3: Implement new GICv4 redistributor registers
Implement the new GICv4 redistributor registers: GICR_VPROPBASER and GICR_VPENDBASER; for the moment we implement these as simple reads-as-written stubs, together with the necessary migration and reset handling. We don't put ID-register checks on the handling of these registers, because they are all in the only-in-v4 extra register frames, so they're not accessible in a GICv3. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-24-peter.maydell@linaro.org
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ae3b3ba15c
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641be69745
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@ -144,6 +144,25 @@ const VMStateDescription vmstate_gicv3_cpu_sre_el1 = {
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}
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}
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};
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};
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static bool gicv4_needed(void *opaque)
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{
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GICv3CPUState *cs = opaque;
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return cs->gic->revision > 3;
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}
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const VMStateDescription vmstate_gicv3_gicv4 = {
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.name = "arm_gicv3_cpu/gicv4",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = gicv4_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(gicr_vpropbaser, GICv3CPUState),
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VMSTATE_UINT64(gicr_vpendbaser, GICv3CPUState),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_gicv3_cpu = {
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static const VMStateDescription vmstate_gicv3_cpu = {
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.name = "arm_gicv3_cpu",
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.name = "arm_gicv3_cpu",
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.version_id = 1,
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.version_id = 1,
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@ -175,6 +194,7 @@ static const VMStateDescription vmstate_gicv3_cpu = {
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.subsections = (const VMStateDescription * []) {
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.subsections = (const VMStateDescription * []) {
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&vmstate_gicv3_cpu_virt,
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&vmstate_gicv3_cpu_virt,
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&vmstate_gicv3_cpu_sre_el1,
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&vmstate_gicv3_cpu_sre_el1,
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&vmstate_gicv3_gicv4,
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NULL
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NULL
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}
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}
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};
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};
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@ -444,6 +464,8 @@ static void arm_gicv3_common_reset(DeviceState *dev)
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cs->gicr_waker = GICR_WAKER_ProcessorSleep | GICR_WAKER_ChildrenAsleep;
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cs->gicr_waker = GICR_WAKER_ProcessorSleep | GICR_WAKER_ChildrenAsleep;
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cs->gicr_propbaser = 0;
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cs->gicr_propbaser = 0;
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cs->gicr_pendbaser = 0;
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cs->gicr_pendbaser = 0;
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cs->gicr_vpropbaser = 0;
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cs->gicr_vpendbaser = 0;
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/* If we're resetting a TZ-aware GIC as if secure firmware
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/* If we're resetting a TZ-aware GIC as if secure firmware
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* had set it up ready to start a kernel in non-secure, we
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* had set it up ready to start a kernel in non-secure, we
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* need to set interrupts to group 1 so the kernel can use them.
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* need to set interrupts to group 1 so the kernel can use them.
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@ -236,6 +236,23 @@ static MemTxResult gicr_readl(GICv3CPUState *cs, hwaddr offset,
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case GICR_IDREGS ... GICR_IDREGS + 0x2f:
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case GICR_IDREGS ... GICR_IDREGS + 0x2f:
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*data = gicv3_idreg(offset - GICR_IDREGS, GICV3_PIDR0_REDIST);
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*data = gicv3_idreg(offset - GICR_IDREGS, GICV3_PIDR0_REDIST);
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return MEMTX_OK;
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return MEMTX_OK;
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/*
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* VLPI frame registers. We don't need a version check for
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* VPROPBASER and VPENDBASER because gicv3_redist_size() will
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* prevent pre-v4 GIC from passing us offsets this high.
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*/
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case GICR_VPROPBASER:
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*data = extract64(cs->gicr_vpropbaser, 0, 32);
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return MEMTX_OK;
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case GICR_VPROPBASER + 4:
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*data = extract64(cs->gicr_vpropbaser, 32, 32);
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return MEMTX_OK;
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case GICR_VPENDBASER:
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*data = extract64(cs->gicr_vpendbaser, 0, 32);
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return MEMTX_OK;
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case GICR_VPENDBASER + 4:
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*data = extract64(cs->gicr_vpendbaser, 32, 32);
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return MEMTX_OK;
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default:
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default:
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return MEMTX_ERROR;
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return MEMTX_ERROR;
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}
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}
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@ -379,6 +396,23 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset,
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"%s: invalid guest write to RO register at offset "
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"%s: invalid guest write to RO register at offset "
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TARGET_FMT_plx "\n", __func__, offset);
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TARGET_FMT_plx "\n", __func__, offset);
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return MEMTX_OK;
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return MEMTX_OK;
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/*
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* VLPI frame registers. We don't need a version check for
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* VPROPBASER and VPENDBASER because gicv3_redist_size() will
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* prevent pre-v4 GIC from passing us offsets this high.
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*/
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case GICR_VPROPBASER:
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cs->gicr_vpropbaser = deposit64(cs->gicr_vpropbaser, 0, 32, value);
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return MEMTX_OK;
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case GICR_VPROPBASER + 4:
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cs->gicr_vpropbaser = deposit64(cs->gicr_vpropbaser, 32, 32, value);
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return MEMTX_OK;
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case GICR_VPENDBASER:
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cs->gicr_vpendbaser = deposit64(cs->gicr_vpendbaser, 0, 32, value);
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return MEMTX_OK;
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case GICR_VPENDBASER + 4:
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cs->gicr_vpendbaser = deposit64(cs->gicr_vpendbaser, 32, 32, value);
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return MEMTX_OK;
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default:
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default:
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return MEMTX_ERROR;
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return MEMTX_ERROR;
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}
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}
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@ -397,6 +431,17 @@ static MemTxResult gicr_readll(GICv3CPUState *cs, hwaddr offset,
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case GICR_PENDBASER:
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case GICR_PENDBASER:
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*data = cs->gicr_pendbaser;
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*data = cs->gicr_pendbaser;
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return MEMTX_OK;
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return MEMTX_OK;
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/*
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* VLPI frame registers. We don't need a version check for
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* VPROPBASER and VPENDBASER because gicv3_redist_size() will
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* prevent pre-v4 GIC from passing us offsets this high.
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*/
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case GICR_VPROPBASER:
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*data = cs->gicr_vpropbaser;
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return MEMTX_OK;
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case GICR_VPENDBASER:
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*data = cs->gicr_vpendbaser;
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return MEMTX_OK;
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default:
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default:
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return MEMTX_ERROR;
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return MEMTX_ERROR;
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}
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}
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@ -418,6 +463,17 @@ static MemTxResult gicr_writell(GICv3CPUState *cs, hwaddr offset,
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"%s: invalid guest write to RO register at offset "
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"%s: invalid guest write to RO register at offset "
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TARGET_FMT_plx "\n", __func__, offset);
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TARGET_FMT_plx "\n", __func__, offset);
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return MEMTX_OK;
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return MEMTX_OK;
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/*
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* VLPI frame registers. We don't need a version check for
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* VPROPBASER and VPENDBASER because gicv3_redist_size() will
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* prevent pre-v4 GIC from passing us offsets this high.
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*/
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case GICR_VPROPBASER:
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cs->gicr_vpropbaser = value;
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return MEMTX_OK;
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case GICR_VPENDBASER:
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cs->gicr_vpendbaser = value;
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return MEMTX_OK;
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default:
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default:
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return MEMTX_ERROR;
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return MEMTX_ERROR;
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}
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}
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@ -77,6 +77,7 @@
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* Redistributor frame offsets from RD_base
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* Redistributor frame offsets from RD_base
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*/
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*/
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#define GICR_SGI_OFFSET 0x10000
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#define GICR_SGI_OFFSET 0x10000
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#define GICR_VLPI_OFFSET 0x20000
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/*
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/*
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* Redistributor registers, offsets from RD_base
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* Redistributor registers, offsets from RD_base
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@ -109,6 +110,10 @@
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#define GICR_IGRPMODR0 (GICR_SGI_OFFSET + 0x0D00)
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#define GICR_IGRPMODR0 (GICR_SGI_OFFSET + 0x0D00)
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#define GICR_NSACR (GICR_SGI_OFFSET + 0x0E00)
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#define GICR_NSACR (GICR_SGI_OFFSET + 0x0E00)
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/* VLPI redistributor registers, offsets from VLPI_base */
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#define GICR_VPROPBASER (GICR_VLPI_OFFSET + 0x70)
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#define GICR_VPENDBASER (GICR_VLPI_OFFSET + 0x78)
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#define GICR_CTLR_ENABLE_LPIS (1U << 0)
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#define GICR_CTLR_ENABLE_LPIS (1U << 0)
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#define GICR_CTLR_CES (1U << 1)
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#define GICR_CTLR_CES (1U << 1)
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#define GICR_CTLR_RWP (1U << 3)
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#define GICR_CTLR_RWP (1U << 3)
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@ -143,6 +148,22 @@ FIELD(GICR_PENDBASER, PTZ, 62, 1)
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#define GICR_PROPBASER_IDBITS_THRESHOLD 0xd
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#define GICR_PROPBASER_IDBITS_THRESHOLD 0xd
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/* These are the GICv4 VPROPBASER and VPENDBASER layouts; v4.1 is different */
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FIELD(GICR_VPROPBASER, IDBITS, 0, 5)
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FIELD(GICR_VPROPBASER, INNERCACHE, 7, 3)
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FIELD(GICR_VPROPBASER, SHAREABILITY, 10, 2)
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FIELD(GICR_VPROPBASER, PHYADDR, 12, 40)
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FIELD(GICR_VPROPBASER, OUTERCACHE, 56, 3)
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FIELD(GICR_VPENDBASER, INNERCACHE, 7, 3)
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FIELD(GICR_VPENDBASER, SHAREABILITY, 10, 2)
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FIELD(GICR_VPENDBASER, PHYADDR, 16, 36)
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FIELD(GICR_VPENDBASER, OUTERCACHE, 56, 3)
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FIELD(GICR_VPENDBASER, DIRTY, 60, 1)
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FIELD(GICR_VPENDBASER, PENDINGLAST, 61, 1)
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FIELD(GICR_VPENDBASER, IDAI, 62, 1)
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FIELD(GICR_VPENDBASER, VALID, 63, 1)
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#define ICC_CTLR_EL1_CBPR (1U << 0)
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#define ICC_CTLR_EL1_CBPR (1U << 0)
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#define ICC_CTLR_EL1_EOIMODE (1U << 1)
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#define ICC_CTLR_EL1_EOIMODE (1U << 1)
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#define ICC_CTLR_EL1_PMHE (1U << 6)
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#define ICC_CTLR_EL1_PMHE (1U << 6)
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@ -179,6 +179,9 @@ struct GICv3CPUState {
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uint32_t gicr_igrpmodr0;
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uint32_t gicr_igrpmodr0;
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uint32_t gicr_nsacr;
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uint32_t gicr_nsacr;
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uint8_t gicr_ipriorityr[GIC_INTERNAL];
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uint8_t gicr_ipriorityr[GIC_INTERNAL];
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/* VLPI_base page registers */
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uint64_t gicr_vpropbaser;
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uint64_t gicr_vpendbaser;
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/* CPU interface */
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/* CPU interface */
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uint64_t icc_sre_el1;
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uint64_t icc_sre_el1;
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