mirror of https://github.com/xemu-project/xemu.git
target/i386: implement SYSCALL/SYSRET in 32-bit emulators
AMD supports both 32-bit and 64-bit SYSCALL/SYSRET, but the TCG only exposes it for 64-bit targets. For system emulation just reuse the helper; for user-mode emulation the ABI is the same as "int $80". The BSDs does not support any fast system call mechanism in 32-bit mode so add to bsd-user the same stub that FreeBSD has for 64-bit compatibility mode. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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6750485bf4
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63fd8ef080
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@ -164,6 +164,10 @@ static inline void target_cpu_loop(CPUX86State *env)
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}
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break;
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case EXCP_SYSCALL:
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/* doesn't do anything */
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break;
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case EXCP_INTERRUPT:
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/* just indicate that signals should be handled asap */
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break;
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@ -211,6 +211,9 @@ void cpu_loop(CPUX86State *env)
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switch(trapnr) {
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case 0x80:
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#ifndef TARGET_X86_64
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case EXCP_SYSCALL:
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#endif
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/* linux syscall from int $0x80 */
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ret = do_syscall(env,
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env->regs[R_EAX],
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@ -227,9 +230,9 @@ void cpu_loop(CPUX86State *env)
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env->regs[R_EAX] = ret;
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}
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break;
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#ifndef TARGET_ABI32
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#ifdef TARGET_X86_64
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case EXCP_SYSCALL:
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/* linux syscall from syscall instruction */
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/* linux syscall from syscall instruction. */
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ret = do_syscall(env,
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env->regs[R_EAX],
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env->regs[R_EDI],
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@ -245,8 +248,6 @@ void cpu_loop(CPUX86State *env)
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env->regs[R_EAX] = ret;
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}
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break;
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#endif
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#ifdef TARGET_X86_64
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case EXCP_VSYSCALL:
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emulate_vsyscall(env);
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break;
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@ -637,7 +637,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
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CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER */
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#ifdef TARGET_X86_64
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#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
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#define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM
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#else
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#define TCG_EXT2_X86_64_FEATURES 0
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#endif
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@ -645,7 +645,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
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#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
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CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
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CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
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TCG_EXT2_X86_64_FEATURES)
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CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES)
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#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
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CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \
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CPUID_EXT3_3DNOWPREFETCH)
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@ -51,10 +51,8 @@ DEF_HELPER_FLAGS_2(get_dr, TCG_CALL_NO_WG, tl, env, int)
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DEF_HELPER_1(sysenter, void, env)
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DEF_HELPER_2(sysexit, void, env, int)
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#ifdef TARGET_X86_64
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DEF_HELPER_2(syscall, void, env, int)
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DEF_HELPER_2(sysret, void, env, int)
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#endif
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DEF_HELPER_FLAGS_2(pause, TCG_CALL_NO_WG, noreturn, env, int)
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DEF_HELPER_FLAGS_3(raise_interrupt, TCG_CALL_NO_WG, noreturn, env, int, int)
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DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, int)
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@ -977,6 +977,7 @@ static void do_interrupt64(CPUX86State *env, int intno, int is_int,
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e2);
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env->eip = offset;
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}
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#endif /* TARGET_X86_64 */
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void helper_sysret(CPUX86State *env, int dflag)
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{
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@ -990,6 +991,7 @@ void helper_sysret(CPUX86State *env, int dflag)
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raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
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}
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selector = (env->star >> 48) & 0xffff;
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#ifdef TARGET_X86_64
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if (env->hflags & HF_LMA_MASK) {
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cpu_load_eflags(env, (uint32_t)(env->regs[11]), TF_MASK | AC_MASK
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| ID_MASK | IF_MASK | IOPL_MASK | VM_MASK | RF_MASK |
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@ -1015,7 +1017,9 @@ void helper_sysret(CPUX86State *env, int dflag)
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DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
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DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
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DESC_W_MASK | DESC_A_MASK);
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} else {
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} else
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#endif
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{
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env->eflags |= IF_MASK;
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cpu_x86_load_seg_cache(env, R_CS, selector | 3,
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0, 0xffffffff,
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@ -1030,7 +1034,6 @@ void helper_sysret(CPUX86State *env, int dflag)
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DESC_W_MASK | DESC_A_MASK);
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}
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}
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#endif /* TARGET_X86_64 */
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/* real mode interrupt */
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static void do_interrupt_real(CPUX86State *env, int intno, int is_int,
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@ -26,7 +26,6 @@
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#include "tcg/helper-tcg.h"
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#include "../seg_helper.h"
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#ifdef TARGET_X86_64
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void helper_syscall(CPUX86State *env, int next_eip_addend)
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{
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int selector;
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@ -35,6 +34,7 @@ void helper_syscall(CPUX86State *env, int next_eip_addend)
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raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());
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}
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selector = (env->star >> 32) & 0xffff;
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#ifdef TARGET_X86_64
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if (env->hflags & HF_LMA_MASK) {
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int code64;
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@ -61,7 +61,9 @@ void helper_syscall(CPUX86State *env, int next_eip_addend)
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} else {
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env->eip = env->cstar;
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}
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} else {
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} else
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#endif
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{
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env->regs[R_ECX] = (uint32_t)(env->eip + next_eip_addend);
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env->eflags &= ~(IF_MASK | RF_MASK | VM_MASK);
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@ -78,7 +80,6 @@ void helper_syscall(CPUX86State *env, int next_eip_addend)
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env->eip = (uint32_t)env->star;
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}
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}
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#endif /* TARGET_X86_64 */
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void handle_even_inj(CPUX86State *env, int intno, int is_int,
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int error_code, int is_hw, int rm)
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@ -5704,7 +5704,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
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s->base.is_jmp = DISAS_EOB_ONLY;
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}
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break;
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#ifdef TARGET_X86_64
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case 0x105: /* syscall */
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/* For Intel SYSCALL is only valid in long mode */
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if (!LMA(s) && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1) {
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@ -5738,7 +5737,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
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gen_eob_worker(s, false, true);
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}
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break;
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#endif
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case 0x1a2: /* cpuid */
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gen_update_cc_op(s);
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gen_update_eip_cur(s);
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@ -26,7 +26,6 @@
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#include "tcg/helper-tcg.h"
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#include "tcg/seg_helper.h"
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#ifdef TARGET_X86_64
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void helper_syscall(CPUX86State *env, int next_eip_addend)
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{
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CPUState *cs = env_cpu(env);
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env->exception_next_eip = env->eip + next_eip_addend;
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cpu_loop_exit(cs);
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}
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#endif /* TARGET_X86_64 */
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/*
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* fake user mode interrupt. is_int is TRUE if coming from the int
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