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target/hppa: Decode d for sub instructions 

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-09-16 21:25:44 -07:00
parent faf97ba157
commit 63c427c615
2 changed files with 17 additions and 17 deletions
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12
target/hppa/insns.decode
View File

@ -172,12 +172,12 @@ add_tsv 000010 ..... ..... .... 1110.. . ..... @rrr_cf_d_sh
add_c 000010 ..... ..... .... 011100 . ..... @rrr_cf_d_sh0
add_c_tsv 000010 ..... ..... .... 111100 . ..... @rrr_cf_d_sh0
sub 000010 ..... ..... .... 010000 - ..... @rrr_cf
sub_tsv 000010 ..... ..... .... 110000 0 ..... @rrr_cf
sub_tc 000010 ..... ..... .... 010011 0 ..... @rrr_cf
sub_tsv_tc 000010 ..... ..... .... 110011 0 ..... @rrr_cf
sub_b 000010 ..... ..... .... 010100 0 ..... @rrr_cf
sub_b_tsv 000010 ..... ..... .... 110100 0 ..... @rrr_cf
sub 000010 ..... ..... .... 010000 . ..... @rrr_cf_d
sub_tsv 000010 ..... ..... .... 110000 . ..... @rrr_cf_d
sub_tc 000010 ..... ..... .... 010011 . ..... @rrr_cf_d
sub_tsv_tc 000010 ..... ..... .... 110011 . ..... @rrr_cf_d
sub_b 000010 ..... ..... .... 010100 . ..... @rrr_cf_d
sub_b_tsv 000010 ..... ..... .... 110100 . ..... @rrr_cf_d
ldil 001000 t:5 ..................... i=%assemble_21
addil 001010 r:5 ..................... i=%assemble_21

22
target/hppa/translate.c
View File

@ -1287,12 +1287,11 @@ static bool do_add_imm(DisasContext *ctx, arg_rri_cf *a,
static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1,
TCGv_reg in2, bool is_tsv, bool is_b,
bool is_tc, unsigned cf)
bool is_tc, unsigned cf, bool d)
{
TCGv_reg dest, sv, cb, cb_msb, zero, tmp;
unsigned c = cf >> 1;
DisasCond cond;
bool d = false;
dest = tcg_temp_new();
cb = tcg_temp_new();
@ -1350,7 +1349,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1,
ctx->null_cond = cond;
}
static bool do_sub_reg(DisasContext *ctx, arg_rrr_cf *a,
static bool do_sub_reg(DisasContext *ctx, arg_rrr_cf_d *a,
bool is_tsv, bool is_b, bool is_tc)
{
TCGv_reg tcg_r1, tcg_r2;
@ -1360,7 +1359,7 @@ static bool do_sub_reg(DisasContext *ctx, arg_rrr_cf *a,
}
tcg_r1 = load_gpr(ctx, a->r1);
tcg_r2 = load_gpr(ctx, a->r2);
do_sub(ctx, a->t, tcg_r1, tcg_r2, is_tsv, is_b, is_tc, a->cf);
do_sub(ctx, a->t, tcg_r1, tcg_r2, is_tsv, is_b, is_tc, a->cf, a->d);
return nullify_end(ctx);
}
@ -1373,7 +1372,8 @@ static bool do_sub_imm(DisasContext *ctx, arg_rri_cf *a, bool is_tsv)
}
tcg_im = tcg_constant_reg(a->i);
tcg_r2 = load_gpr(ctx, a->r);
do_sub(ctx, a->t, tcg_im, tcg_r2, is_tsv, 0, 0, a->cf);
/* All SUBI conditions are 32-bit. */
do_sub(ctx, a->t, tcg_im, tcg_r2, is_tsv, 0, 0, a->cf, false);
return nullify_end(ctx);
}
@ -2661,32 +2661,32 @@ static bool trans_add_c_tsv(DisasContext *ctx, arg_rrr_cf_d_sh *a)
return do_add_reg(ctx, a, false, true, false, true);
}
static bool trans_sub(DisasContext *ctx, arg_rrr_cf *a)
static bool trans_sub(DisasContext *ctx, arg_rrr_cf_d *a)
{
return do_sub_reg(ctx, a, false, false, false);
}
static bool trans_sub_tsv(DisasContext *ctx, arg_rrr_cf *a)
static bool trans_sub_tsv(DisasContext *ctx, arg_rrr_cf_d *a)
{
return do_sub_reg(ctx, a, true, false, false);
}
static bool trans_sub_tc(DisasContext *ctx, arg_rrr_cf *a)
static bool trans_sub_tc(DisasContext *ctx, arg_rrr_cf_d *a)
{
return do_sub_reg(ctx, a, false, false, true);
}
static bool trans_sub_tsv_tc(DisasContext *ctx, arg_rrr_cf *a)
static bool trans_sub_tsv_tc(DisasContext *ctx, arg_rrr_cf_d *a)
{
return do_sub_reg(ctx, a, true, false, true);
}
static bool trans_sub_b(DisasContext *ctx, arg_rrr_cf *a)
static bool trans_sub_b(DisasContext *ctx, arg_rrr_cf_d *a)
{
return do_sub_reg(ctx, a, false, true, false);
}
static bool trans_sub_b_tsv(DisasContext *ctx, arg_rrr_cf *a)
static bool trans_sub_b_tsv(DisasContext *ctx, arg_rrr_cf_d *a)
{
return do_sub_reg(ctx, a, true, true, false);
}