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target/xtensa: add parity/ECC option SRs 

Add SRs and rsr/wsr/xsr opcodes defined by the parity/ECC xtensa option.
The implementation is trivial since we don't emulate parity/ECC yet.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2019-03-13 12:41:13 -07:00
parent 944bb3320a
commit 631a77a03b
3 changed files with 170 additions and 0 deletions
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6
target/xtensa/cpu.h
View File

@ -144,6 +144,12 @@ enum {
CACHEATTR = 98, CACHEATTR = 98,
ATOMCTL = 99, ATOMCTL = 99,
DDR = 104, DDR = 104,
MEPC = 106,
MEPS = 107,
MESAVE = 108,
MESR = 109,
MECR = 110,
MEVADDR = 111,
IBREAKA = 128, IBREAKA = 128,
DBREAKA = 144, DBREAKA = 144,
DBREAKC = 160, DBREAKC = 160,

2
target/xtensa/overlay_tool.h
View File

@ -112,6 +112,8 @@
XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \ XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \
XTENSA_OPTION_DCACHE_INDEX_LOCK) | \ XTENSA_OPTION_DCACHE_INDEX_LOCK) | \
XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \ XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \
XCHAL_OPTION(XCHAL_HAVE_MEM_ECC_PARITY, \
XTENSA_OPTION_MEMORY_ECC_PARITY) | \
/* Memory protection and translation */ \ /* Memory protection and translation */ \
XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \ XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \
XTENSA_OPTION_REGION_PROTECTION) | \ XTENSA_OPTION_REGION_PROTECTION) | \

162
target/xtensa/translate.c
View File

@ -4215,6 +4215,60 @@ static const XtensaOpcodeOps core_ops[] = {
.translate = translate_rsr, .translate = translate_rsr,
.par = (const uint32_t[]){MEMCTL}, .par = (const uint32_t[]){MEMCTL},
.op_flags = XTENSA_OP_PRIVILEGED, .op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "rsr.mecr",
.translate = translate_rsr,
.test_ill = test_ill_sr,
.par = (const uint32_t[]){
MECR,
XTENSA_OPTION_MEMORY_ECC_PARITY,
},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "rsr.mepc",
.translate = translate_rsr,
.test_ill = test_ill_sr,
.par = (const uint32_t[]){
MEPC,
XTENSA_OPTION_MEMORY_ECC_PARITY,
},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "rsr.meps",
.translate = translate_rsr,
.test_ill = test_ill_sr,
.par = (const uint32_t[]){
MEPS,
XTENSA_OPTION_MEMORY_ECC_PARITY,
},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "rsr.mesave",
.translate = translate_rsr,
.test_ill = test_ill_sr,
.par = (const uint32_t[]){
MESAVE,
XTENSA_OPTION_MEMORY_ECC_PARITY,
},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "rsr.mesr",
.translate = translate_rsr,
.test_ill = test_ill_sr,
.par = (const uint32_t[]){
MESR,
XTENSA_OPTION_MEMORY_ECC_PARITY,
},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "rsr.mevaddr",
.translate = translate_rsr,
.test_ill = test_ill_sr,
.par = (const uint32_t[]){
MESR,
XTENSA_OPTION_MEMORY_ECC_PARITY,
},
.op_flags = XTENSA_OP_PRIVILEGED,
}, { }, {
.name = "rsr.misc0", .name = "rsr.misc0",
.translate = translate_rsr, .translate = translate_rsr,
@ -5035,6 +5089,60 @@ static const XtensaOpcodeOps core_ops[] = {
.translate = translate_wsr_memctl, .translate = translate_wsr_memctl,
.par = (const uint32_t[]){MEMCTL}, .par = (const uint32_t[]){MEMCTL},
.op_flags = XTENSA_OP_PRIVILEGED, .op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "wsr.mecr",
.translate = translate_wsr,
.test_ill = test_ill_sr,
.par = (const uint32_t[]){
MECR,
XTENSA_OPTION_MEMORY_ECC_PARITY,
},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "wsr.mepc",
.translate = translate_wsr,
.test_ill = test_ill_sr,
.par = (const uint32_t[]){
MEPC,
XTENSA_OPTION_MEMORY_ECC_PARITY,
},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "wsr.meps",
.translate = translate_wsr,
.test_ill = test_ill_sr,
.par = (const uint32_t[]){
MEPS,
XTENSA_OPTION_MEMORY_ECC_PARITY,
},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "wsr.mesave",
.translate = translate_wsr,
.test_ill = test_ill_sr,
.par = (const uint32_t[]){
MESAVE,
XTENSA_OPTION_MEMORY_ECC_PARITY,
},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "wsr.mesr",
.translate = translate_wsr,
.test_ill = test_ill_sr,
.par = (const uint32_t[]){
MESR,
XTENSA_OPTION_MEMORY_ECC_PARITY,
},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "wsr.mevaddr",
.translate = translate_wsr,
.test_ill = test_ill_sr,
.par = (const uint32_t[]){
MESR,
XTENSA_OPTION_MEMORY_ECC_PARITY,
},
.op_flags = XTENSA_OP_PRIVILEGED,
}, { }, {
.name = "wsr.misc0", .name = "wsr.misc0",
.translate = translate_wsr, .translate = translate_wsr,
@ -5701,6 +5809,60 @@ static const XtensaOpcodeOps core_ops[] = {
.translate = translate_xsr_memctl, .translate = translate_xsr_memctl,
.par = (const uint32_t[]){MEMCTL}, .par = (const uint32_t[]){MEMCTL},
.op_flags = XTENSA_OP_PRIVILEGED, .op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "xsr.mecr",
.translate = translate_xsr,
.test_ill = test_ill_sr,
.par = (const uint32_t[]){
MECR,
XTENSA_OPTION_MEMORY_ECC_PARITY,
},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "xsr.mepc",
.translate = translate_xsr,
.test_ill = test_ill_sr,
.par = (const uint32_t[]){
MEPC,
XTENSA_OPTION_MEMORY_ECC_PARITY,
},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "xsr.meps",
.translate = translate_xsr,
.test_ill = test_ill_sr,
.par = (const uint32_t[]){
MEPS,
XTENSA_OPTION_MEMORY_ECC_PARITY,
},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "xsr.mesave",
.translate = translate_xsr,
.test_ill = test_ill_sr,
.par = (const uint32_t[]){
MESAVE,
XTENSA_OPTION_MEMORY_ECC_PARITY,
},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "xsr.mesr",
.translate = translate_xsr,
.test_ill = test_ill_sr,
.par = (const uint32_t[]){
MESR,
XTENSA_OPTION_MEMORY_ECC_PARITY,
},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "xsr.mevaddr",
.translate = translate_xsr,
.test_ill = test_ill_sr,
.par = (const uint32_t[]){
MESR,
XTENSA_OPTION_MEMORY_ECC_PARITY,
},
.op_flags = XTENSA_OP_PRIVILEGED,
}, { }, {
.name = "xsr.misc0", .name = "xsr.misc0",
.translate = translate_xsr, .translate = translate_xsr,