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exynos: Fix bad printf format specifiers 

We should use printf format specifier "%u" instead of "%d" for
argument of type "unsigned int".

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Alex Chen <alex.chen@huawei.com>
Message-id: 20201111073651.72804-1-alex.chen@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Alex Chen 2020-11-17 12:56:32 +00:00 committed by Peter Maydell
parent 3362c56835
commit 63192565f9
2 changed files with 6 additions and 6 deletions
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4
hw/timer/exynos4210_mct.c
View File

@ -537,7 +537,7 @@ static void exynos4210_gcomp_raise_irq(void *opaque, uint32_t id)
/* If CSTAT is pending and IRQ is enabled */ /* If CSTAT is pending and IRQ is enabled */
if ((s->reg.int_cstat & G_INT_CSTAT_COMP(id)) && if ((s->reg.int_cstat & G_INT_CSTAT_COMP(id)) &&
(s->reg.int_enb & G_INT_ENABLE(id))) { (s->reg.int_enb & G_INT_ENABLE(id))) {
DPRINTF("gcmp timer[%d] IRQ\n", id); DPRINTF("gcmp timer[%u] IRQ\n", id);
qemu_irq_raise(s->irq[id]); qemu_irq_raise(s->irq[id]);
} }
} }
@ -1003,7 +1003,7 @@ static void exynos4210_mct_update_freq(Exynos4210MCTState *s)
MCT_CFG_GET_DIVIDER(s->reg_mct_cfg)); MCT_CFG_GET_DIVIDER(s->reg_mct_cfg));
if (freq != s->freq) { if (freq != s->freq) {
DPRINTF("freq=%dHz\n", s->freq); DPRINTF("freq=%uHz\n", s->freq);
/* global timer */ /* global timer */
tx_ptimer_set_freq(s->g_timer.ptimer_frc, s->freq); tx_ptimer_set_freq(s->g_timer.ptimer_frc, s->freq);

8
hw/timer/exynos4210_pwm.c
View File

@ -169,7 +169,7 @@ static void exynos4210_pwm_update_freq(Exynos4210PWMState *s, uint32_t id)
if (freq != s->timer[id].freq) { if (freq != s->timer[id].freq) {
ptimer_set_freq(s->timer[id].ptimer, s->timer[id].freq); ptimer_set_freq(s->timer[id].ptimer, s->timer[id].freq);
DPRINTF("freq=%dHz\n", s->timer[id].freq); DPRINTF("freq=%uHz\n", s->timer[id].freq);
} }
} }
@ -183,14 +183,14 @@ static void exynos4210_pwm_tick(void *opaque)
uint32_t id = s->id; uint32_t id = s->id;
bool cmp; bool cmp;
DPRINTF("timer %d tick\n", id); DPRINTF("timer %u tick\n", id);
/* set irq status */ /* set irq status */
p->reg_tint_cstat |= TINT_CSTAT_STATUS(id); p->reg_tint_cstat |= TINT_CSTAT_STATUS(id);
/* raise IRQ */ /* raise IRQ */
if (p->reg_tint_cstat & TINT_CSTAT_ENABLE(id)) { if (p->reg_tint_cstat & TINT_CSTAT_ENABLE(id)) {
DPRINTF("timer %d IRQ\n", id); DPRINTF("timer %u IRQ\n", id);
qemu_irq_raise(p->timer[id].irq); qemu_irq_raise(p->timer[id].irq);
} }
@ -202,7 +202,7 @@ static void exynos4210_pwm_tick(void *opaque)
} }
if (cmp) { if (cmp) {
DPRINTF("auto reload timer %d count to %x\n", id, DPRINTF("auto reload timer %u count to %x\n", id,
p->timer[id].reg_tcntb); p->timer[id].reg_tcntb);
ptimer_set_count(p->timer[id].ptimer, p->timer[id].reg_tcntb); ptimer_set_count(p->timer[id].ptimer, p->timer[id].reg_tcntb);
ptimer_run(p->timer[id].ptimer, 1); ptimer_run(p->timer[id].ptimer, 1);