From 62a09b9b4118ca42e79d9bd179daf7230462705b Mon Sep 17 00:00:00 2001 From: Weiwei Li Date: Mon, 18 Jul 2022 21:09:54 +0800 Subject: [PATCH] target/riscv: Fix checks in hmode/hmode32 Add check for the implicit dependence between H and S Csrs only existed in RV32 will not trigger virtual instruction fault when not in RV32 based on section 8.6.1 of riscv-privileged spec (draft-20220717) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Message-Id: <20220718130955.11899-6-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 5 +++++ target/riscv/csr.c | 9 ++------- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fb37ffac64..117d308ae5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -733,6 +733,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } + if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { + error_setg(errp, "H extension implicitly requires S-mode"); + return; + } + if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { error_setg(errp, "F extension requires Zicsr"); return; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5c69dc838c..cf15aa67b7 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -311,8 +311,7 @@ static int aia_smode32(CPURISCVState *env, int csrno) static RISCVException hmode(CPURISCVState *env, int csrno) { - if (riscv_has_ext(env, RVS) && - riscv_has_ext(env, RVH)) { + if (riscv_has_ext(env, RVH)) { /* Hypervisor extension is supported */ if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || env->priv == PRV_M) { @@ -328,11 +327,7 @@ static RISCVException hmode(CPURISCVState *env, int csrno) static RISCVException hmode32(CPURISCVState *env, int csrno) { if (riscv_cpu_mxl(env) != MXL_RV32) { - if (!riscv_cpu_virt_enabled(env)) { - return RISCV_EXCP_ILLEGAL_INST; - } else { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } + return RISCV_EXCP_ILLEGAL_INST; } return hmode(env, csrno);