mirror of https://github.com/xemu-project/xemu.git
target/loongarch: Implement LASX fpu fcvt instructions
This patch includes:
- XVFCVT{L/H}.{S.H/D.S};
- XVFCVT.{H.S/S.D};
- XVFRINT[{RNE/RZ/RP/RM}].{S/D};
- XVFTINT[{RNE/RZ/RP/RM}].{W.S/L.D};
- XVFTINT[RZ].{WU.S/LU.D};
- XVFTINT[{RNE/RZ/RP/RM}].W.D;
- XVFTINT[{RNE/RZ/RP/RM}]{L/H}.L.S;
- XVFFINT.{S.W/D.L}[U];
- X[CVFFINT.S.L, VFFINT{L/H}.D.W.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914022645.1151356-48-gaosong@loongson.cn>
This commit is contained in:
Song Gao
parent
c9caf1587a
commit
60df31a207
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@ -2286,6 +2286,62 @@ INSN_LASX(xvfrecip_d, vv)
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INSN_LASX(xvfrsqrt_s, vv)
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INSN_LASX(xvfrsqrt_d, vv)
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INSN_LASX(xvfcvtl_s_h, vv)
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INSN_LASX(xvfcvth_s_h, vv)
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INSN_LASX(xvfcvtl_d_s, vv)
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INSN_LASX(xvfcvth_d_s, vv)
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INSN_LASX(xvfcvt_h_s, vvv)
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INSN_LASX(xvfcvt_s_d, vvv)
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INSN_LASX(xvfrint_s, vv)
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INSN_LASX(xvfrint_d, vv)
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INSN_LASX(xvfrintrm_s, vv)
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INSN_LASX(xvfrintrm_d, vv)
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INSN_LASX(xvfrintrp_s, vv)
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INSN_LASX(xvfrintrp_d, vv)
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INSN_LASX(xvfrintrz_s, vv)
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INSN_LASX(xvfrintrz_d, vv)
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INSN_LASX(xvfrintrne_s, vv)
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INSN_LASX(xvfrintrne_d, vv)
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INSN_LASX(xvftint_w_s, vv)
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INSN_LASX(xvftint_l_d, vv)
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INSN_LASX(xvftintrm_w_s, vv)
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INSN_LASX(xvftintrm_l_d, vv)
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INSN_LASX(xvftintrp_w_s, vv)
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INSN_LASX(xvftintrp_l_d, vv)
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INSN_LASX(xvftintrz_w_s, vv)
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INSN_LASX(xvftintrz_l_d, vv)
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INSN_LASX(xvftintrne_w_s, vv)
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INSN_LASX(xvftintrne_l_d, vv)
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INSN_LASX(xvftint_wu_s, vv)
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INSN_LASX(xvftint_lu_d, vv)
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INSN_LASX(xvftintrz_wu_s, vv)
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INSN_LASX(xvftintrz_lu_d, vv)
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INSN_LASX(xvftint_w_d, vvv)
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INSN_LASX(xvftintrm_w_d, vvv)
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INSN_LASX(xvftintrp_w_d, vvv)
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INSN_LASX(xvftintrz_w_d, vvv)
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INSN_LASX(xvftintrne_w_d, vvv)
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INSN_LASX(xvftintl_l_s, vv)
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INSN_LASX(xvftinth_l_s, vv)
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INSN_LASX(xvftintrml_l_s, vv)
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INSN_LASX(xvftintrmh_l_s, vv)
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INSN_LASX(xvftintrpl_l_s, vv)
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INSN_LASX(xvftintrph_l_s, vv)
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INSN_LASX(xvftintrzl_l_s, vv)
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INSN_LASX(xvftintrzh_l_s, vv)
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INSN_LASX(xvftintrnel_l_s, vv)
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INSN_LASX(xvftintrneh_l_s, vv)
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INSN_LASX(xvffint_s_w, vv)
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INSN_LASX(xvffint_s_wu, vv)
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INSN_LASX(xvffint_d_l, vv)
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INSN_LASX(xvffint_d_lu, vv)
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INSN_LASX(xvffintl_d_w, vv)
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INSN_LASX(xvffinth_d_w, vv)
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INSN_LASX(xvffint_s_l, vvv)
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INSN_LASX(xvreplgr2vr_b, vr)
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INSN_LASX(xvreplgr2vr_h, vr)
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INSN_LASX(xvreplgr2vr_w, vr)
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@ -4403,6 +4403,12 @@ TRANS(vfcvtl_d_s, LSX, gen_vv_ptr, gen_helper_vfcvtl_d_s)
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TRANS(vfcvth_d_s, LSX, gen_vv_ptr, gen_helper_vfcvth_d_s)
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TRANS(vfcvt_h_s, LSX, gen_vvv_ptr, gen_helper_vfcvt_h_s)
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TRANS(vfcvt_s_d, LSX, gen_vvv_ptr, gen_helper_vfcvt_s_d)
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TRANS(xvfcvtl_s_h, LASX, gen_xx_ptr, gen_helper_vfcvtl_s_h)
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TRANS(xvfcvth_s_h, LASX, gen_xx_ptr, gen_helper_vfcvth_s_h)
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TRANS(xvfcvtl_d_s, LASX, gen_xx_ptr, gen_helper_vfcvtl_d_s)
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TRANS(xvfcvth_d_s, LASX, gen_xx_ptr, gen_helper_vfcvth_d_s)
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TRANS(xvfcvt_h_s, LASX, gen_xxx_ptr, gen_helper_vfcvt_h_s)
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TRANS(xvfcvt_s_d, LASX, gen_xxx_ptr, gen_helper_vfcvt_s_d)
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TRANS(vfrintrne_s, LSX, gen_vv_ptr, gen_helper_vfrintrne_s)
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TRANS(vfrintrne_d, LSX, gen_vv_ptr, gen_helper_vfrintrne_d)
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@ -4414,6 +4420,16 @@ TRANS(vfrintrm_s, LSX, gen_vv_ptr, gen_helper_vfrintrm_s)
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TRANS(vfrintrm_d, LSX, gen_vv_ptr, gen_helper_vfrintrm_d)
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TRANS(vfrint_s, LSX, gen_vv_ptr, gen_helper_vfrint_s)
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TRANS(vfrint_d, LSX, gen_vv_ptr, gen_helper_vfrint_d)
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TRANS(xvfrintrne_s, LASX, gen_xx_ptr, gen_helper_vfrintrne_s)
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TRANS(xvfrintrne_d, LASX, gen_xx_ptr, gen_helper_vfrintrne_d)
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TRANS(xvfrintrz_s, LASX, gen_xx_ptr, gen_helper_vfrintrz_s)
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TRANS(xvfrintrz_d, LASX, gen_xx_ptr, gen_helper_vfrintrz_d)
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TRANS(xvfrintrp_s, LASX, gen_xx_ptr, gen_helper_vfrintrp_s)
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TRANS(xvfrintrp_d, LASX, gen_xx_ptr, gen_helper_vfrintrp_d)
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TRANS(xvfrintrm_s, LASX, gen_xx_ptr, gen_helper_vfrintrm_s)
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TRANS(xvfrintrm_d, LASX, gen_xx_ptr, gen_helper_vfrintrm_d)
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TRANS(xvfrint_s, LASX, gen_xx_ptr, gen_helper_vfrint_s)
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TRANS(xvfrint_d, LASX, gen_xx_ptr, gen_helper_vfrint_d)
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TRANS(vftintrne_w_s, LSX, gen_vv_ptr, gen_helper_vftintrne_w_s)
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TRANS(vftintrne_l_d, LSX, gen_vv_ptr, gen_helper_vftintrne_l_d)
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@ -4444,6 +4460,35 @@ TRANS(vftintrml_l_s, LSX, gen_vv_ptr, gen_helper_vftintrml_l_s)
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TRANS(vftintrmh_l_s, LSX, gen_vv_ptr, gen_helper_vftintrmh_l_s)
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TRANS(vftintl_l_s, LSX, gen_vv_ptr, gen_helper_vftintl_l_s)
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TRANS(vftinth_l_s, LSX, gen_vv_ptr, gen_helper_vftinth_l_s)
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TRANS(xvftintrne_w_s, LASX, gen_xx_ptr, gen_helper_vftintrne_w_s)
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TRANS(xvftintrne_l_d, LASX, gen_xx_ptr, gen_helper_vftintrne_l_d)
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TRANS(xvftintrz_w_s, LASX, gen_xx_ptr, gen_helper_vftintrz_w_s)
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TRANS(xvftintrz_l_d, LASX, gen_xx_ptr, gen_helper_vftintrz_l_d)
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TRANS(xvftintrp_w_s, LASX, gen_xx_ptr, gen_helper_vftintrp_w_s)
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TRANS(xvftintrp_l_d, LASX, gen_xx_ptr, gen_helper_vftintrp_l_d)
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TRANS(xvftintrm_w_s, LASX, gen_xx_ptr, gen_helper_vftintrm_w_s)
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TRANS(xvftintrm_l_d, LASX, gen_xx_ptr, gen_helper_vftintrm_l_d)
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TRANS(xvftint_w_s, LASX, gen_xx_ptr, gen_helper_vftint_w_s)
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TRANS(xvftint_l_d, LASX, gen_xx_ptr, gen_helper_vftint_l_d)
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TRANS(xvftintrz_wu_s, LASX, gen_xx_ptr, gen_helper_vftintrz_wu_s)
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TRANS(xvftintrz_lu_d, LASX, gen_xx_ptr, gen_helper_vftintrz_lu_d)
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TRANS(xvftint_wu_s, LASX, gen_xx_ptr, gen_helper_vftint_wu_s)
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TRANS(xvftint_lu_d, LASX, gen_xx_ptr, gen_helper_vftint_lu_d)
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TRANS(xvftintrne_w_d, LASX, gen_xxx_ptr, gen_helper_vftintrne_w_d)
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TRANS(xvftintrz_w_d, LASX, gen_xxx_ptr, gen_helper_vftintrz_w_d)
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TRANS(xvftintrp_w_d, LASX, gen_xxx_ptr, gen_helper_vftintrp_w_d)
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TRANS(xvftintrm_w_d, LASX, gen_xxx_ptr, gen_helper_vftintrm_w_d)
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TRANS(xvftint_w_d, LASX, gen_xxx_ptr, gen_helper_vftint_w_d)
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TRANS(xvftintrnel_l_s, LASX, gen_xx_ptr, gen_helper_vftintrnel_l_s)
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TRANS(xvftintrneh_l_s, LASX, gen_xx_ptr, gen_helper_vftintrneh_l_s)
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TRANS(xvftintrzl_l_s, LASX, gen_xx_ptr, gen_helper_vftintrzl_l_s)
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TRANS(xvftintrzh_l_s, LASX, gen_xx_ptr, gen_helper_vftintrzh_l_s)
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TRANS(xvftintrpl_l_s, LASX, gen_xx_ptr, gen_helper_vftintrpl_l_s)
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TRANS(xvftintrph_l_s, LASX, gen_xx_ptr, gen_helper_vftintrph_l_s)
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TRANS(xvftintrml_l_s, LASX, gen_xx_ptr, gen_helper_vftintrml_l_s)
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TRANS(xvftintrmh_l_s, LASX, gen_xx_ptr, gen_helper_vftintrmh_l_s)
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TRANS(xvftintl_l_s, LASX, gen_xx_ptr, gen_helper_vftintl_l_s)
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TRANS(xvftinth_l_s, LASX, gen_xx_ptr, gen_helper_vftinth_l_s)
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TRANS(vffint_s_w, LSX, gen_vv_ptr, gen_helper_vffint_s_w)
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TRANS(vffint_d_l, LSX, gen_vv_ptr, gen_helper_vffint_d_l)
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@ -4452,6 +4497,13 @@ TRANS(vffint_d_lu, LSX, gen_vv_ptr, gen_helper_vffint_d_lu)
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TRANS(vffintl_d_w, LSX, gen_vv_ptr, gen_helper_vffintl_d_w)
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TRANS(vffinth_d_w, LSX, gen_vv_ptr, gen_helper_vffinth_d_w)
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TRANS(vffint_s_l, LSX, gen_vvv_ptr, gen_helper_vffint_s_l)
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TRANS(xvffint_s_w, LASX, gen_xx_ptr, gen_helper_vffint_s_w)
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TRANS(xvffint_d_l, LASX, gen_xx_ptr, gen_helper_vffint_d_l)
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TRANS(xvffint_s_wu, LASX, gen_xx_ptr, gen_helper_vffint_s_wu)
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TRANS(xvffint_d_lu, LASX, gen_xx_ptr, gen_helper_vffint_d_lu)
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TRANS(xvffintl_d_w, LASX, gen_xx_ptr, gen_helper_vffintl_d_w)
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TRANS(xvffinth_d_w, LASX, gen_xx_ptr, gen_helper_vffinth_d_w)
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TRANS(xvffint_s_l, LASX, gen_xxx_ptr, gen_helper_vffint_s_l)
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static bool do_cmp(DisasContext *ctx, arg_vvv *a, MemOp mop, TCGCond cond)
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{
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@ -1857,6 +1857,64 @@ xvfrecip_d 0111 01101001 11001 11110 ..... ..... @vv
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xvfrsqrt_s 0111 01101001 11010 00001 ..... ..... @vv
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xvfrsqrt_d 0111 01101001 11010 00010 ..... ..... @vv
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xvfcvtl_s_h 0111 01101001 11011 11010 ..... ..... @vv
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xvfcvth_s_h 0111 01101001 11011 11011 ..... ..... @vv
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xvfcvtl_d_s 0111 01101001 11011 11100 ..... ..... @vv
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xvfcvth_d_s 0111 01101001 11011 11101 ..... ..... @vv
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xvfcvt_h_s 0111 01010100 01100 ..... ..... ..... @vvv
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xvfcvt_s_d 0111 01010100 01101 ..... ..... ..... @vvv
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xvfrintrne_s 0111 01101001 11010 11101 ..... ..... @vv
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xvfrintrne_d 0111 01101001 11010 11110 ..... ..... @vv
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xvfrintrz_s 0111 01101001 11010 11001 ..... ..... @vv
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xvfrintrz_d 0111 01101001 11010 11010 ..... ..... @vv
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xvfrintrp_s 0111 01101001 11010 10101 ..... ..... @vv
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xvfrintrp_d 0111 01101001 11010 10110 ..... ..... @vv
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xvfrintrm_s 0111 01101001 11010 10001 ..... ..... @vv
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xvfrintrm_d 0111 01101001 11010 10010 ..... ..... @vv
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xvfrint_s 0111 01101001 11010 01101 ..... ..... @vv
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xvfrint_d 0111 01101001 11010 01110 ..... ..... @vv
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xvftintrne_w_s 0111 01101001 11100 10100 ..... ..... @vv
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xvftintrne_l_d 0111 01101001 11100 10101 ..... ..... @vv
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xvftintrz_w_s 0111 01101001 11100 10010 ..... ..... @vv
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xvftintrz_l_d 0111 01101001 11100 10011 ..... ..... @vv
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xvftintrp_w_s 0111 01101001 11100 10000 ..... ..... @vv
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xvftintrp_l_d 0111 01101001 11100 10001 ..... ..... @vv
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xvftintrm_w_s 0111 01101001 11100 01110 ..... ..... @vv
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xvftintrm_l_d 0111 01101001 11100 01111 ..... ..... @vv
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xvftint_w_s 0111 01101001 11100 01100 ..... ..... @vv
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xvftint_l_d 0111 01101001 11100 01101 ..... ..... @vv
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xvftintrz_wu_s 0111 01101001 11100 11100 ..... ..... @vv
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xvftintrz_lu_d 0111 01101001 11100 11101 ..... ..... @vv
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xvftint_wu_s 0111 01101001 11100 10110 ..... ..... @vv
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xvftint_lu_d 0111 01101001 11100 10111 ..... ..... @vv
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xvftintrne_w_d 0111 01010100 10111 ..... ..... ..... @vvv
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xvftintrz_w_d 0111 01010100 10110 ..... ..... ..... @vvv
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xvftintrp_w_d 0111 01010100 10101 ..... ..... ..... @vvv
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xvftintrm_w_d 0111 01010100 10100 ..... ..... ..... @vvv
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xvftint_w_d 0111 01010100 10011 ..... ..... ..... @vvv
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xvftintrnel_l_s 0111 01101001 11101 01000 ..... ..... @vv
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xvftintrneh_l_s 0111 01101001 11101 01001 ..... ..... @vv
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xvftintrzl_l_s 0111 01101001 11101 00110 ..... ..... @vv
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xvftintrzh_l_s 0111 01101001 11101 00111 ..... ..... @vv
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xvftintrpl_l_s 0111 01101001 11101 00100 ..... ..... @vv
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xvftintrph_l_s 0111 01101001 11101 00101 ..... ..... @vv
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xvftintrml_l_s 0111 01101001 11101 00010 ..... ..... @vv
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xvftintrmh_l_s 0111 01101001 11101 00011 ..... ..... @vv
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xvftintl_l_s 0111 01101001 11101 00000 ..... ..... @vv
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xvftinth_l_s 0111 01101001 11101 00001 ..... ..... @vv
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xvffint_s_w 0111 01101001 11100 00000 ..... ..... @vv
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xvffint_d_l 0111 01101001 11100 00010 ..... ..... @vv
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xvffint_s_wu 0111 01101001 11100 00001 ..... ..... @vv
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xvffint_d_lu 0111 01101001 11100 00011 ..... ..... @vv
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xvffintl_d_w 0111 01101001 11100 00100 ..... ..... @vv
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xvffinth_d_w 0111 01101001 11100 00101 ..... ..... @vv
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xvffint_s_l 0111 01010100 10000 ..... ..... ..... @vvv
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xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr
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xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr
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xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr
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@ -2624,14 +2624,19 @@ static uint32_t float64_cvt_float32(uint64_t d, float_status *status)
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void HELPER(vfcvtl_s_h)(void *vd, void *vj,
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CPULoongArchState *env, uint32_t desc)
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{
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int i;
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VReg temp;
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int i, j, ofs;
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VReg temp = {};
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VReg *Vd = (VReg *)vd;
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VReg *Vj = (VReg *)vj;
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int oprsz = simd_oprsz(desc);
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ofs = LSX_LEN / 32;
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vec_clear_cause(env);
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for (i = 0; i < LSX_LEN/32; i++) {
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temp.UW(i) = float16_cvt_float32(Vj->UH(i), &env->fp_status);
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for (i = 0; i < oprsz / 16; i++) {
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for (j = 0; j < ofs; j++) {
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temp.UW(j + ofs * i) =float16_cvt_float32(Vj->UH(j + ofs * 2 * i),
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&env->fp_status);
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}
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vec_update_fcsr0(env, GETPC());
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}
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*Vd = temp;
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@ -2640,14 +2645,19 @@ void HELPER(vfcvtl_s_h)(void *vd, void *vj,
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void HELPER(vfcvtl_d_s)(void *vd, void *vj,
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CPULoongArchState *env, uint32_t desc)
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{
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int i;
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VReg temp;
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int i, j, ofs;
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VReg temp = {};
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VReg *Vd = (VReg *)vd;
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VReg *Vj = (VReg *)vj;
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int oprsz = simd_oprsz(desc);
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ofs = LSX_LEN / 64;
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vec_clear_cause(env);
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for (i = 0; i < LSX_LEN/64; i++) {
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temp.UD(i) = float32_cvt_float64(Vj->UW(i), &env->fp_status);
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for (i = 0; i < oprsz / 16; i++) {
|
||||
for (j = 0; j < ofs; j++) {
|
||||
temp.UD(j + ofs * i) = float32_cvt_float64(Vj->UW(j + ofs * 2 * i),
|
||||
&env->fp_status);
|
||||
}
|
||||
vec_update_fcsr0(env, GETPC());
|
||||
}
|
||||
*Vd = temp;
|
||||
|
|
@ -2656,14 +2666,19 @@ void HELPER(vfcvtl_d_s)(void *vd, void *vj,
|
|||
void HELPER(vfcvth_s_h)(void *vd, void *vj,
|
||||
CPULoongArchState *env, uint32_t desc)
|
||||
{
|
||||
int i;
|
||||
VReg temp;
|
||||
int i, j, ofs;
|
||||
VReg temp = {};
|
||||
VReg *Vd = (VReg *)vd;
|
||||
VReg *Vj = (VReg *)vj;
|
||||
int oprsz = simd_oprsz(desc);
|
||||
|
||||
ofs = LSX_LEN / 32;
|
||||
vec_clear_cause(env);
|
||||
for (i = 0; i < LSX_LEN/32; i++) {
|
||||
temp.UW(i) = float16_cvt_float32(Vj->UH(i + 4), &env->fp_status);
|
||||
for (i = 0; i < oprsz / 16; i++) {
|
||||
for (j = 0; j < ofs; j++) {
|
||||
temp.UW(j + ofs * i) = float16_cvt_float32(Vj->UH(j + ofs * (2 * i + 1)),
|
||||
&env->fp_status);
|
||||
}
|
||||
vec_update_fcsr0(env, GETPC());
|
||||
}
|
||||
*Vd = temp;
|
||||
|
|
@ -2672,14 +2687,19 @@ void HELPER(vfcvth_s_h)(void *vd, void *vj,
|
|||
void HELPER(vfcvth_d_s)(void *vd, void *vj,
|
||||
CPULoongArchState *env, uint32_t desc)
|
||||
{
|
||||
int i;
|
||||
VReg temp;
|
||||
int i, j, ofs;
|
||||
VReg temp = {};
|
||||
VReg *Vd = (VReg *)vd;
|
||||
VReg *Vj = (VReg *)vj;
|
||||
int oprsz = simd_oprsz(desc);
|
||||
|
||||
ofs = LSX_LEN / 64;
|
||||
vec_clear_cause(env);
|
||||
for (i = 0; i < LSX_LEN/64; i++) {
|
||||
temp.UD(i) = float32_cvt_float64(Vj->UW(i + 2), &env->fp_status);
|
||||
for (i = 0; i < oprsz / 16; i++) {
|
||||
for (j = 0; j < ofs; j++) {
|
||||
temp.UD(j + ofs * i) = float32_cvt_float64(Vj->UW(j + ofs * (2 * i + 1)),
|
||||
&env->fp_status);
|
||||
}
|
||||
vec_update_fcsr0(env, GETPC());
|
||||
}
|
||||
*Vd = temp;
|
||||
|
|
@ -2688,16 +2708,22 @@ void HELPER(vfcvth_d_s)(void *vd, void *vj,
|
|||
void HELPER(vfcvt_h_s)(void *vd, void *vj, void *vk,
|
||||
CPULoongArchState *env, uint32_t desc)
|
||||
{
|
||||
int i;
|
||||
VReg temp;
|
||||
int i, j, ofs;
|
||||
VReg temp = {};
|
||||
VReg *Vd = (VReg *)vd;
|
||||
VReg *Vj = (VReg *)vj;
|
||||
VReg *Vk = (VReg *)vk;
|
||||
int oprsz = simd_oprsz(desc);
|
||||
|
||||
ofs = LSX_LEN / 32;
|
||||
vec_clear_cause(env);
|
||||
for(i = 0; i < LSX_LEN/32; i++) {
|
||||
temp.UH(i + 4) = float32_cvt_float16(Vj->UW(i), &env->fp_status);
|
||||
temp.UH(i) = float32_cvt_float16(Vk->UW(i), &env->fp_status);
|
||||
for(i = 0; i < oprsz / 16; i++) {
|
||||
for (j = 0; j < ofs; j++) {
|
||||
temp.UH(j + ofs * (2 * i + 1)) = float32_cvt_float16(Vj->UW(j + ofs * i),
|
||||
&env->fp_status);
|
||||
temp.UH(j + ofs * 2 * i) = float32_cvt_float16(Vk->UW(j + ofs * i),
|
||||
&env->fp_status);
|
||||
}
|
||||
vec_update_fcsr0(env, GETPC());
|
||||
}
|
||||
*Vd = temp;
|
||||
|
|
@ -2706,16 +2732,22 @@ void HELPER(vfcvt_h_s)(void *vd, void *vj, void *vk,
|
|||
void HELPER(vfcvt_s_d)(void *vd, void *vj, void *vk,
|
||||
CPULoongArchState *env, uint32_t desc)
|
||||
{
|
||||
int i;
|
||||
VReg temp;
|
||||
int i, j, ofs;
|
||||
VReg temp = {};
|
||||
VReg *Vd = (VReg *)vd;
|
||||
VReg *Vj = (VReg *)vj;
|
||||
VReg *Vk = (VReg *)vk;
|
||||
int oprsz = simd_oprsz(desc);
|
||||
|
||||
ofs = LSX_LEN / 64;
|
||||
vec_clear_cause(env);
|
||||
for(i = 0; i < LSX_LEN/64; i++) {
|
||||
temp.UW(i + 2) = float64_cvt_float32(Vj->UD(i), &env->fp_status);
|
||||
temp.UW(i) = float64_cvt_float32(Vk->UD(i), &env->fp_status);
|
||||
for(i = 0; i < oprsz / 16; i++) {
|
||||
for (j = 0; j < ofs; j++) {
|
||||
temp.UW(j + ofs * (2 * i + 1)) = float64_cvt_float32(Vj->UD(j + ofs * i),
|
||||
&env->fp_status);
|
||||
temp.UW(j + ofs * 2 * i) = float64_cvt_float32(Vk->UD(j + ofs * i),
|
||||
&env->fp_status);
|
||||
}
|
||||
vec_update_fcsr0(env, GETPC());
|
||||
}
|
||||
*Vd = temp;
|
||||
|
|
@ -2727,9 +2759,10 @@ void HELPER(vfrint_s)(void *vd, void *vj,
|
|||
int i;
|
||||
VReg *Vd = (VReg *)vd;
|
||||
VReg *Vj = (VReg *)vj;
|
||||
int oprsz = simd_oprsz(desc);
|
||||
|
||||
vec_clear_cause(env);
|
||||
for (i = 0; i < 4; i++) {
|
||||
for (i = 0; i < oprsz / 4; i++) {
|
||||
Vd->W(i) = float32_round_to_int(Vj->UW(i), &env->fp_status);
|
||||
vec_update_fcsr0(env, GETPC());
|
||||
}
|
||||
|
|
@ -2741,9 +2774,10 @@ void HELPER(vfrint_d)(void *vd, void *vj,
|
|||
int i;
|
||||
VReg *Vd = (VReg *)vd;
|
||||
VReg *Vj = (VReg *)vj;
|
||||
int oprsz = simd_oprsz(desc);
|
||||
|
||||
vec_clear_cause(env);
|
||||
for (i = 0; i < 2; i++) {
|
||||
for (i = 0; i < oprsz / 8; i++) {
|
||||
Vd->D(i) = float64_round_to_int(Vj->UD(i), &env->fp_status);
|
||||
vec_update_fcsr0(env, GETPC());
|
||||
}
|
||||
|
|
@ -2756,9 +2790,10 @@ void HELPER(NAME)(void *vd, void *vj, \
|
|||
int i; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
int oprsz = simd_oprsz(desc); \
|
||||
\
|
||||
vec_clear_cause(env); \
|
||||
for (i = 0; i < LSX_LEN/BIT; i++) { \
|
||||
for (i = 0; i < oprsz / (BIT / 8); i++) { \
|
||||
FloatRoundMode old_mode = get_float_rounding_mode(&env->fp_status); \
|
||||
set_float_rounding_mode(MODE, &env->fp_status); \
|
||||
Vd->E(i) = float## BIT ## _round_to_int(Vj->E(i), &env->fp_status); \
|
||||
|
|
@ -2843,22 +2878,26 @@ FTINT(rp_w_d, float64, int32, uint64_t, uint32_t, float_round_up)
|
|||
FTINT(rz_w_d, float64, int32, uint64_t, uint32_t, float_round_to_zero)
|
||||
FTINT(rne_w_d, float64, int32, uint64_t, uint32_t, float_round_nearest_even)
|
||||
|
||||
#define FTINT_W_D(NAME, FN) \
|
||||
void HELPER(NAME)(void *vd, void *vj, void *vk, \
|
||||
CPULoongArchState *env, uint32_t desc) \
|
||||
{ \
|
||||
int i; \
|
||||
VReg temp; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
VReg *Vk = (VReg *)vk; \
|
||||
\
|
||||
vec_clear_cause(env); \
|
||||
for (i = 0; i < 2; i++) { \
|
||||
temp.W(i + 2) = FN(env, Vj->UD(i)); \
|
||||
temp.W(i) = FN(env, Vk->UD(i)); \
|
||||
} \
|
||||
*Vd = temp; \
|
||||
#define FTINT_W_D(NAME, FN) \
|
||||
void HELPER(NAME)(void *vd, void *vj, void *vk, \
|
||||
CPULoongArchState *env, uint32_t desc) \
|
||||
{ \
|
||||
int i, j, ofs; \
|
||||
VReg temp = {}; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
VReg *Vk = (VReg *)vk; \
|
||||
int oprsz = simd_oprsz(desc); \
|
||||
\
|
||||
ofs = LSX_LEN / 64; \
|
||||
vec_clear_cause(env); \
|
||||
for (i = 0; i < oprsz / 16; i++) { \
|
||||
for (j = 0; j < ofs; j++) { \
|
||||
temp.W(j + ofs * (2 * i + 1)) = FN(env, Vj->UD(j + ofs * i)); \
|
||||
temp.W(j + ofs * 2 * i) = FN(env, Vk->UD(j + ofs * i)); \
|
||||
} \
|
||||
} \
|
||||
*Vd = temp; \
|
||||
}
|
||||
|
||||
FTINT_W_D(vftint_w_d, do_float64_to_int32)
|
||||
|
|
@ -2876,20 +2915,24 @@ FTINT(rph_l_s, float32, int64, uint32_t, uint64_t, float_round_up)
|
|||
FTINT(rzh_l_s, float32, int64, uint32_t, uint64_t, float_round_to_zero)
|
||||
FTINT(rneh_l_s, float32, int64, uint32_t, uint64_t, float_round_nearest_even)
|
||||
|
||||
#define FTINTL_L_S(NAME, FN) \
|
||||
void HELPER(NAME)(void *vd, void *vj, \
|
||||
CPULoongArchState *env, uint32_t desc) \
|
||||
{ \
|
||||
int i; \
|
||||
VReg temp; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
\
|
||||
vec_clear_cause(env); \
|
||||
for (i = 0; i < 2; i++) { \
|
||||
temp.D(i) = FN(env, Vj->UW(i)); \
|
||||
} \
|
||||
*Vd = temp; \
|
||||
#define FTINTL_L_S(NAME, FN) \
|
||||
void HELPER(NAME)(void *vd, void *vj, \
|
||||
CPULoongArchState *env, uint32_t desc) \
|
||||
{ \
|
||||
int i, j, ofs; \
|
||||
VReg temp; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
int oprsz = simd_oprsz(desc); \
|
||||
\
|
||||
ofs = LSX_LEN / 64; \
|
||||
vec_clear_cause(env); \
|
||||
for (i = 0; i < oprsz / 16; i++) { \
|
||||
for (j = 0; j < ofs; j++) { \
|
||||
temp.D(j + ofs * i) = FN(env, Vj->UW(j + ofs * 2 * i)); \
|
||||
} \
|
||||
} \
|
||||
*Vd = temp; \
|
||||
}
|
||||
|
||||
FTINTL_L_S(vftintl_l_s, do_float32_to_int64)
|
||||
|
|
@ -2898,20 +2941,24 @@ FTINTL_L_S(vftintrpl_l_s, do_ftintrpl_l_s)
|
|||
FTINTL_L_S(vftintrzl_l_s, do_ftintrzl_l_s)
|
||||
FTINTL_L_S(vftintrnel_l_s, do_ftintrnel_l_s)
|
||||
|
||||
#define FTINTH_L_S(NAME, FN) \
|
||||
void HELPER(NAME)(void *vd, void *vj, \
|
||||
CPULoongArchState *env, uint32_t desc) \
|
||||
{ \
|
||||
int i; \
|
||||
VReg temp; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
\
|
||||
vec_clear_cause(env); \
|
||||
for (i = 0; i < 2; i++) { \
|
||||
temp.D(i) = FN(env, Vj->UW(i + 2)); \
|
||||
} \
|
||||
*Vd = temp; \
|
||||
#define FTINTH_L_S(NAME, FN) \
|
||||
void HELPER(NAME)(void *vd, void *vj, \
|
||||
CPULoongArchState *env, uint32_t desc) \
|
||||
{ \
|
||||
int i, j, ofs; \
|
||||
VReg temp = {}; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
int oprsz = simd_oprsz(desc); \
|
||||
\
|
||||
ofs = LSX_LEN / 64; \
|
||||
vec_clear_cause(env); \
|
||||
for (i = 0; i < oprsz / 16; i++) { \
|
||||
for (j = 0; j < ofs; j++) { \
|
||||
temp.D(j + ofs * i) = FN(env, Vj->UW(j + ofs * (2 * i + 1))); \
|
||||
} \
|
||||
} \
|
||||
*Vd = temp; \
|
||||
}
|
||||
|
||||
FTINTH_L_S(vftinth_l_s, do_float32_to_int64)
|
||||
|
|
@ -2943,14 +2990,19 @@ DO_2OP_F(vffint_d_lu, 64, UD, do_ffint_d_lu)
|
|||
void HELPER(vffintl_d_w)(void *vd, void *vj,
|
||||
CPULoongArchState *env, uint32_t desc)
|
||||
{
|
||||
int i;
|
||||
VReg temp;
|
||||
int i, j, ofs;
|
||||
VReg temp = {};
|
||||
VReg *Vd = (VReg *)vd;
|
||||
VReg *Vj = (VReg *)vj;
|
||||
int oprsz = simd_oprsz(desc);
|
||||
|
||||
ofs = LSX_LEN / 64;
|
||||
vec_clear_cause(env);
|
||||
for (i = 0; i < 2; i++) {
|
||||
temp.D(i) = int32_to_float64(Vj->W(i), &env->fp_status);
|
||||
for (i = 0; i < oprsz / 16; i++) {
|
||||
for (j = 0; j < ofs; j++) {
|
||||
temp.D(j + ofs * i) = int32_to_float64(Vj->W(j + ofs * 2 * i),
|
||||
&env->fp_status);
|
||||
}
|
||||
vec_update_fcsr0(env, GETPC());
|
||||
}
|
||||
*Vd = temp;
|
||||
|
|
@ -2959,14 +3011,19 @@ void HELPER(vffintl_d_w)(void *vd, void *vj,
|
|||
void HELPER(vffinth_d_w)(void *vd, void *vj,
|
||||
CPULoongArchState *env, uint32_t desc)
|
||||
{
|
||||
int i;
|
||||
VReg temp;
|
||||
int i, j, ofs;
|
||||
VReg temp = {};
|
||||
VReg *Vd = (VReg *)vd;
|
||||
VReg *Vj = (VReg *)vj;
|
||||
int oprsz = simd_oprsz(desc);
|
||||
|
||||
ofs = LSX_LEN / 64;
|
||||
vec_clear_cause(env);
|
||||
for (i = 0; i < 2; i++) {
|
||||
temp.D(i) = int32_to_float64(Vj->W(i + 2), &env->fp_status);
|
||||
for (i = 0; i < oprsz /16; i++) {
|
||||
for (j = 0; j < ofs; j++) {
|
||||
temp.D(j + ofs * i) = int32_to_float64(Vj->W(j + ofs * (2 * i + 1)),
|
||||
&env->fp_status);
|
||||
}
|
||||
vec_update_fcsr0(env, GETPC());
|
||||
}
|
||||
*Vd = temp;
|
||||
|
|
@ -2975,16 +3032,22 @@ void HELPER(vffinth_d_w)(void *vd, void *vj,
|
|||
void HELPER(vffint_s_l)(void *vd, void *vj, void *vk,
|
||||
CPULoongArchState *env, uint32_t desc)
|
||||
{
|
||||
int i;
|
||||
VReg temp;
|
||||
int i, j, ofs;
|
||||
VReg temp = {};
|
||||
VReg *Vd = (VReg *)vd;
|
||||
VReg *Vj = (VReg *)vj;
|
||||
VReg *Vk = (VReg *)vk;
|
||||
int oprsz = simd_oprsz(desc);
|
||||
|
||||
ofs = LSX_LEN / 64;
|
||||
vec_clear_cause(env);
|
||||
for (i = 0; i < 2; i++) {
|
||||
temp.W(i + 2) = int64_to_float32(Vj->D(i), &env->fp_status);
|
||||
temp.W(i) = int64_to_float32(Vk->D(i), &env->fp_status);
|
||||
for (i = 0; i < oprsz / 16; i++) {
|
||||
for (j = 0; j < ofs; j++) {
|
||||
temp.W(j + ofs * (2 * i + 1)) = int64_to_float32(Vj->D(j + ofs * i),
|
||||
&env->fp_status);
|
||||
temp.W(j + ofs * 2 * i) = int64_to_float32(Vk->D(j + ofs * i),
|
||||
&env->fp_status);
|
||||
}
|
||||
vec_update_fcsr0(env, GETPC());
|
||||
}
|
||||
*Vd = temp;
|
||||
|
|
|
|||
Loading…
Reference in New Issue