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Remove an unused field and fix some non-code typos. 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4222 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
balrog 2008-04-20 01:03:45 +00:00
parent 66230e0dee
commit 601d70b9e5
3 changed files with 5 additions and 6 deletions
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1
hw/twl92230.c
View File

@ -62,7 +62,6 @@ struct menelaus_s {
int sec_offset; int sec_offset;
int alm_sec; int alm_sec;
int next_comp; int next_comp;
struct tm *(*gettime)(const time_t *timep, struct tm *result);
} rtc; } rtc;
qemu_irq handler[3]; qemu_irq handler[3];
qemu_irq *in; qemu_irq *in;

6
target-arm/helper.c
View File

@ -737,7 +737,7 @@ void do_interrupt(CPUARMState *env)
new_mode = ARM_CPU_MODE_SVC; new_mode = ARM_CPU_MODE_SVC;
addr = 0x08; addr = 0x08;
mask = CPSR_I; mask = CPSR_I;
/* The PC already points to the next instructon. */ /* The PC already points to the next instruction. */
offset = 0; offset = 0;
break; break;
case EXCP_BKPT: case EXCP_BKPT:
@ -870,7 +870,7 @@ static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,
type = (desc & 3); type = (desc & 3);
domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3; domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3;
if (type == 0) { if (type == 0) {
/* Secton translation fault. */ /* Section translation fault. */
code = 5; code = 5;
goto do_fault; goto do_fault;
} }
@ -961,7 +961,7 @@ static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type,
desc = ldl_phys(table); desc = ldl_phys(table);
type = (desc & 3); type = (desc & 3);
if (type == 0) { if (type == 0) {
/* Secton translation fault. */ /* Section translation fault. */
code = 5; code = 5;
domain = 0; domain = 0;
goto do_fault; goto do_fault;

4
target-arm/translate.c
View File

@ -2877,7 +2877,7 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
tmp = load_cpu_field(vfp.xregs[rn]); tmp = load_cpu_field(vfp.xregs[rn]);
break; break;
case ARM_VFP_FPSCR: case ARM_VFP_FPSCR:
if (rd == 15) { if (rd == 15) {
tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
tcg_gen_andi_i32(tmp, tmp, 0xf0000000); tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
} else { } else {
@ -6887,7 +6887,7 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
if (!(arm_feature(env, ARM_FEATURE_THUMB2) if (!(arm_feature(env, ARM_FEATURE_THUMB2)
|| arm_feature (env, ARM_FEATURE_M))) { || arm_feature (env, ARM_FEATURE_M))) {
/* Thumb-1 cores may need to tread bl and blx as a pair of /* Thumb-1 cores may need to treat bl and blx as a pair of
16-bit instructions to get correct prefetch abort behavior. */ 16-bit instructions to get correct prefetch abort behavior. */
insn = insn_hw1; insn = insn_hw1;
if ((insn & (1 << 12)) == 0) { if ((insn & (1 << 12)) == 0) {