From 5fe91019e66e2c2187f0af2324e25d450eb03a86 Mon Sep 17 00:00:00 2001 From: Mark Langsdorf Date: Wed, 25 Jan 2012 11:49:46 +0000 Subject: [PATCH] arm: store the config_base_register during cpu_reset Long term, the config_base_register will be a QDM parameter. In the meantime, models that use it need to be able to preserve it across cpu_reset() calls. Signed-off-by: Mark Langsdorf Signed-off-by: Peter Maydell --- target-arm/helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index f6e998b0f7..22e40fc924 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -255,6 +255,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) void cpu_reset(CPUARMState *env) { uint32_t id; + uint32_t tmp = 0; if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); @@ -262,9 +263,11 @@ void cpu_reset(CPUARMState *env) } id = env->cp15.c0_cpuid; + tmp = env->cp15.c15_config_base_address; memset(env, 0, offsetof(CPUARMState, breakpoints)); if (id) cpu_reset_model_id(env, id); + env->cp15.c15_config_base_address = tmp; #if defined (CONFIG_USER_ONLY) env->uncached_cpsr = ARM_CPU_MODE_USR; /* For user mode we must enable access to coprocessors */