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target/arm: implement DBGCLAIM registers 

The architecture does not define any functionality for the CLAIM tag bits.
So we will just keep the raw bits, as per spec.

Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230120155929.32384-2-eiakovlev@linux.microsoft.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Evgeny Iakovlev 2023-01-20 16:59:28 +01:00 committed by Peter Maydell
parent 1e5da7e553
commit 5fc83f1128
2 changed files with 34 additions and 0 deletions
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1
target/arm/cpu.h
View File

@ -495,6 +495,7 @@ typedef struct CPUArchState {
uint64_t dbgbcr[16]; /* breakpoint control registers */
uint64_t dbgwvr[16]; /* watchpoint value registers */
uint64_t dbgwcr[16]; /* watchpoint control registers */
uint64_t dbgclaim; /* DBGCLAIM bits */
uint64_t mdscr_el1;
uint64_t oslsr_el1; /* OS Lock Status */
uint64_t osdlr_el1; /* OS DoubleLock status */

33
target/arm/debug_helper.c
View File

@ -632,6 +632,24 @@ static void osdlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
}
}
static void dbgclaimset_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
env->cp15.dbgclaim |= (value & 0xFF);
}
static uint64_t dbgclaimset_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
/* CLAIM bits are RAO */
return 0xFF;
}
static void dbgclaimclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
env->cp15.dbgclaim &= ~(value & 0xFF);
}
static const ARMCPRegInfo debug_cp_reginfo[] = {
/*
* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
@ -715,6 +733,21 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
.access = PL1_RW, .accessfn = access_tda,
.type = ARM_CP_NOP },
/*
* Dummy DBGCLAIM registers.
* "The architecture does not define any functionality for the CLAIM tag bits.",
* so we only keep the raw bits
*/
{ .name = "DBGCLAIMSET_EL1", .state = ARM_CP_STATE_BOTH,
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 6,
.type = ARM_CP_ALIAS,
.access = PL1_RW, .accessfn = access_tda,
.writefn = dbgclaimset_write, .readfn = dbgclaimset_read },
{ .name = "DBGCLAIMCLR_EL1", .state = ARM_CP_STATE_BOTH,
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 6,
.access = PL1_RW, .accessfn = access_tda,
.writefn = dbgclaimclr_write, .raw_writefn = raw_write,
.fieldoffset = offsetof(CPUARMState, cp15.dbgclaim) },
};
static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {