mirror of https://github.com/xemu-project/xemu.git
target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled
We'll have future usage for a function where, given an offset of the struct RISCVCPUConfig, the flag is updated to a certain val. Change all existing callers to use edata->ext_enable_offset instead of 'edata'. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20230912132423.268494-14-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -162,18 +162,17 @@ static const struct isa_ext_data isa_edata_arr[] = {
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ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
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ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
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};
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};
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static bool isa_ext_is_enabled(RISCVCPU *cpu,
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static bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
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const struct isa_ext_data *edata)
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{
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{
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bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset;
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bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
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return *ext_enabled;
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return *ext_enabled;
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}
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}
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static void isa_ext_update_enabled(RISCVCPU *cpu,
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static void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset,
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const struct isa_ext_data *edata, bool en)
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bool en)
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{
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{
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bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset;
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bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
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*ext_enabled = en;
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*ext_enabled = en;
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}
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}
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@ -1045,9 +1044,10 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
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/* Force disable extensions if priv spec version does not match */
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/* Force disable extensions if priv spec version does not match */
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for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
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for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
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if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) &&
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if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset) &&
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(env->priv_ver < isa_edata_arr[i].min_version)) {
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(env->priv_ver < isa_edata_arr[i].min_version)) {
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isa_ext_update_enabled(cpu, &isa_edata_arr[i], false);
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isa_ext_update_enabled(cpu, isa_edata_arr[i].ext_enable_offset,
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false);
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#ifndef CONFIG_USER_ONLY
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#ifndef CONFIG_USER_ONLY
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warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
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warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
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" because privilege spec version does not match",
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" because privilege spec version does not match",
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@ -2340,7 +2340,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
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int i;
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int i;
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for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
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for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
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if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) {
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if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset)) {
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new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
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new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
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g_free(old);
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g_free(old);
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old = new;
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old = new;
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