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target/sparc: Remove sparcv7 cpu features 

The oldest supported cpu is the microsparc 1; all other cpus
use CPU_DEFAULT_FEATURES.  Remove the features that must always
be present for sparcv7: FLOAT, SWAP, FLUSH, FSQRT, FMUL.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-10-11 20:34:14 -07:00
parent de1f52032f
commit 5f25b383a8
5 changed files with 11 additions and 57 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
linux-user/sparc/target_syscall.h
View File

@ -50,11 +50,7 @@ static inline abi_ulong target_shmlba(CPUSPARCState *env)
#ifdef TARGET_SPARC64
return MAX(TARGET_PAGE_SIZE, 16 * 1024);
#else
if (!(env->def.features & CPU_FEATURE_FLUSH)) {
return 64 * 1024;
} else {
return 256 * 1024;
}
return 256 * 1024;
#endif
}

5
target/sparc/cpu-feature.h.inc
View File

@ -1,11 +1,6 @@
FEATURE(FLOAT)
FEATURE(FLOAT128)
FEATURE(SWAP)
FEATURE(MUL)
FEATURE(DIV)
FEATURE(FLUSH)
FEATURE(FSQRT)
FEATURE(FMUL)
FEATURE(VIS1)
FEATURE(VIS2)
FEATURE(FSMULD)

24
target/sparc/cpu.c
View File

@ -403,9 +403,7 @@ static const sparc_def_t sparc_defs[] = {
.mmu_sfsr_mask = 0x00016fff,
.mmu_trcr_mask = 0x0000003f,
.nwindows = 7,
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL |
CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT |
CPU_FEATURE_FMUL,
.features = CPU_FEATURE_MUL | CPU_FEATURE_DIV,
},
{
.name = "TI MicroSparc II",
@ -547,14 +545,9 @@ static const sparc_def_t sparc_defs[] = {
/* This must match sparc_cpu_properties[]. */
static const char * const feature_name[] = {
[CPU_FEATURE_BIT_FLOAT] = "float",
[CPU_FEATURE_BIT_FLOAT128] = "float128",
[CPU_FEATURE_BIT_SWAP] = "swap",
[CPU_FEATURE_BIT_MUL] = "mul",
[CPU_FEATURE_BIT_DIV] = "div",
[CPU_FEATURE_BIT_FLUSH] = "flush",
[CPU_FEATURE_BIT_FSQRT] = "fsqrt",
[CPU_FEATURE_BIT_FMUL] = "fmul",
[CPU_FEATURE_BIT_VIS1] = "vis1",
[CPU_FEATURE_BIT_VIS2] = "vis2",
[CPU_FEATURE_BIT_FSMULD] = "fsmuld",
@ -758,9 +751,8 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
CPUSPARCState *env = &cpu->env;
#if defined(CONFIG_USER_ONLY)
if ((env->def.features & CPU_FEATURE_FLOAT)) {
env->def.features |= CPU_FEATURE_FLOAT128;
}
/* We are emulating the kernel, which will trap and emulate float128. */
env->def.features |= CPU_FEATURE_FLOAT128;
#endif
env->version = env->def.iu_version;
@ -838,22 +830,12 @@ static PropertyInfo qdev_prop_nwindows = {
/* This must match feature_name[]. */
static Property sparc_cpu_properties[] = {
DEFINE_PROP_BIT("float", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_FLOAT, false),
DEFINE_PROP_BIT("float128", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_FLOAT128, false),
DEFINE_PROP_BIT("swap", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_SWAP, false),
DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_MUL, false),
DEFINE_PROP_BIT("div", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_DIV, false),
DEFINE_PROP_BIT("flush", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_FLUSH, false),
DEFINE_PROP_BIT("fsqrt", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_FSQRT, false),
DEFINE_PROP_BIT("fmul", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_FMUL, false),
DEFINE_PROP_BIT("vis1", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_VIS1, false),
DEFINE_PROP_BIT("vis2", SPARCCPU, env.def.features,

21
target/sparc/cpu.h
View File

@ -306,17 +306,12 @@ enum {
#undef FEATURE
#ifndef TARGET_SPARC64
#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD)
#define CPU_DEFAULT_FEATURES (CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
CPU_FEATURE_FSMULD)
#else
#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \
CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD | \
CPU_FEATURE_CASA)
#define CPU_DEFAULT_FEATURES (CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
CPU_FEATURE_FSMULD | CPU_FEATURE_CASA | \
CPU_FEATURE_VIS1 | CPU_FEATURE_VIS2)
enum {
mmu_us_12, // Ultrasparc < III (64 entry TLB)
mmu_us_3, // Ultrasparc III (512 entry TLB)
@ -799,14 +794,12 @@ static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc,
if (env->pstate & PS_AM) {
flags |= TB_FLAG_AM_ENABLED;
}
if ((env->def.features & CPU_FEATURE_FLOAT)
&& (env->pstate & PS_PEF)
&& (env->fprs & FPRS_FEF)) {
if ((env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) {
flags |= TB_FLAG_FPU_ENABLED;
}
flags |= env->asi << TB_FLAG_ASI_SHIFT;
#else
if ((env->def.features & CPU_FEATURE_FLOAT) && env->psref) {
if (env->psref) {
flags |= TB_FLAG_FPU_ENABLED;
}
#endif

12
target/sparc/translate.c
View File

@ -3527,11 +3527,9 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
gen_ne_fop_FF(dc, rd, rs2, gen_helper_fabss);
break;
case 0x29: /* fsqrts */
CHECK_FPU_FEATURE(dc, FSQRT);
gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts);
break;
case 0x2a: /* fsqrtd */
CHECK_FPU_FEATURE(dc, FSQRT);
gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd);
break;
case 0x2b: /* fsqrtq */
@ -3559,16 +3557,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq);
break;
case 0x49: /* fmuls */
CHECK_FPU_FEATURE(dc, FMUL);
gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fmuls);
break;
case 0x4a: /* fmuld */
CHECK_FPU_FEATURE(dc, FMUL);
gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld);
break;
case 0x4b: /* fmulq */
CHECK_FPU_FEATURE(dc, FLOAT128);
CHECK_FPU_FEATURE(dc, FMUL);
gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq);
break;
case 0x4d: /* fdivs */
@ -5105,8 +5100,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
goto jmp_insn;
#endif
case 0x3b: /* flush */
if (!((dc)->def->features & CPU_FEATURE_FLUSH))
goto unimp_flush;
/* nop */
break;
case 0x3c: /* save */
@ -5224,7 +5217,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
break;
case 0x0f:
/* swap, swap register with memory. Also atomically */
CHECK_IU_FEATURE(dc, SWAP);
cpu_src1 = gen_load_gpr(dc, rd);
gen_swap(dc, cpu_val, cpu_src1, cpu_addr,
dc->mem_idx, MO_TEUL);
@ -5256,7 +5248,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
break;
case 0x1f: /* swapa, swap reg with alt. memory. Also
atomically */
CHECK_IU_FEATURE(dc, SWAP);
cpu_src1 = gen_load_gpr(dc, rd);
gen_swap_asi(dc, cpu_val, cpu_src1, cpu_addr, insn);
break;
@ -5578,9 +5569,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
illegal_insn:
gen_exception(dc, TT_ILL_INSN);
return;
unimp_flush:
gen_exception(dc, TT_UNIMP_FLUSH);
return;
#if !defined(CONFIG_USER_ONLY)
priv_insn:
gen_exception(dc, TT_PRIV_INSN);