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ppc/pnv: Connect I2C controller model to powernv9 chip 

Wires up three I2C controller instances to the powernv9 chip
XSCOM address space.

Each controller instance is wired up to a single I2C bus of
its own.  No other I2C devices are connected to the buses
at this time.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
[milesg: Split wiring from addition of model itself]
[milesg: Added new commit message]
[milesg: Moved hardcoded attributes into PnvChipClass]
[milesg: Removed TODO comment for I2C]
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Acked-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-ID: <20231016222013.3739530-3-milesg@linux.vnet.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Cédric Le Goater 2023-10-16 17:20:13 -05:00 committed by Daniel Henrique Barboza
parent 263b81ee15
commit 5f06612154
2 changed files with 36 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
hw/ppc/pnv.c
View File

@ -1432,6 +1432,10 @@ static void pnv_chip_power9_instance_init(Object *obj)
object_initialize_child(obj, "pec[*]", &chip9->pecs[i], object_initialize_child(obj, "pec[*]", &chip9->pecs[i],
TYPE_PNV_PHB4_PEC); TYPE_PNV_PHB4_PEC);
} }
for (i = 0; i < pcc->i2c_num_engines; i++) {
object_initialize_child(obj, "i2c[*]", &chip9->i2c[i], TYPE_PNV_I2C);
}
} }
static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq,
@ -1504,6 +1508,7 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
PnvChip *chip = PNV_CHIP(dev); PnvChip *chip = PNV_CHIP(dev);
Pnv9Psi *psi9 = &chip9->psi; Pnv9Psi *psi9 = &chip9->psi;
Error *local_err = NULL; Error *local_err = NULL;
int i;
/* XSCOM bridge is first */ /* XSCOM bridge is first */
pnv_xscom_init(chip, PNV9_XSCOM_SIZE, PNV9_XSCOM_BASE(chip)); pnv_xscom_init(chip, PNV9_XSCOM_SIZE, PNV9_XSCOM_BASE(chip));
@ -1602,6 +1607,27 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
error_propagate(errp, local_err); error_propagate(errp, local_err);
return; return;
} }
/*
* I2C
*/
for (i = 0; i < pcc->i2c_num_engines; i++) {
Object *obj = OBJECT(&chip9->i2c[i]);
object_property_set_int(obj, "engine", i + 1, &error_fatal);
object_property_set_int(obj, "num-busses", pcc->i2c_num_ports,
&error_fatal);
object_property_set_link(obj, "chip", OBJECT(chip), &error_abort);
if (!qdev_realize(DEVICE(obj), NULL, errp)) {
return;
}
pnv_xscom_add_subregion(chip, PNV9_XSCOM_I2CM_BASE +
chip9->i2c[i].engine * PNV9_XSCOM_I2CM_SIZE,
&chip9->i2c[i].xscom_regs);
qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0,
qdev_get_gpio_in(DEVICE(&chip9->psi),
PSIHB9_IRQ_SBE_I2C));
}
} }
static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr)
@ -1629,6 +1655,8 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
k->xscom_pcba = pnv_chip_power9_xscom_pcba; k->xscom_pcba = pnv_chip_power9_xscom_pcba;
dc->desc = "PowerNV Chip POWER9"; dc->desc = "PowerNV Chip POWER9";
k->num_pecs = PNV9_CHIP_MAX_PEC; k->num_pecs = PNV9_CHIP_MAX_PEC;
k->i2c_num_engines = PNV9_CHIP_MAX_I2C;
k->i2c_num_ports = PNV9_CHIP_MAX_I2C_PORTS;
device_class_set_parent_realize(dc, pnv_chip_power9_realize, device_class_set_parent_realize(dc, pnv_chip_power9_realize,
&k->parent_realize); &k->parent_realize);

8
include/hw/ppc/pnv_chip.h
View File

@ -9,6 +9,7 @@
#include "hw/ppc/pnv_psi.h" #include "hw/ppc/pnv_psi.h"
#include "hw/ppc/pnv_sbe.h" #include "hw/ppc/pnv_sbe.h"
#include "hw/ppc/pnv_xive.h" #include "hw/ppc/pnv_xive.h"
#include "hw/ppc/pnv_i2c.h"
#include "hw/sysbus.h" #include "hw/sysbus.h"
OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass, OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass,
@ -86,6 +87,10 @@ struct Pnv9Chip {
#define PNV9_CHIP_MAX_PEC 3 #define PNV9_CHIP_MAX_PEC 3
PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC]; PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC];
#define PNV9_CHIP_MAX_I2C 3
#define PNV9_CHIP_MAX_I2C_PORTS 1
PnvI2C i2c[PNV9_CHIP_MAX_I2C];
}; };
/* /*
@ -130,6 +135,9 @@ struct PnvChipClass {
uint32_t num_pecs; uint32_t num_pecs;
uint32_t num_phbs; uint32_t num_phbs;
uint32_t i2c_num_engines;
uint32_t i2c_num_ports;
DeviceRealize parent_realize; DeviceRealize parent_realize;
uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);