mirror of https://github.com/xemu-project/xemu.git
target/riscv: Relax fld alignment requirement
According to the risc-v specification: "FLD and FSD are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN≥64." We currently implement fld as MO_ATOM_IFALIGN when XLEN < 64, which does not violate the rules. But it will hide some problems. So relax it to MO_ATOM_NONE. Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240802072417.659-4-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -48,11 +48,17 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
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REQUIRE_EXT(ctx, RVD);
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REQUIRE_EXT(ctx, RVD);
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/*
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/*
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* Zama16b applies to loads and stores of no more than MXLEN bits defined
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* FLD and FSD are only guaranteed to execute atomically if the effective
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* in the F, D, and Q extensions.
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* address is naturally aligned and XLEN≥64. Also, zama16b applies to
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* loads and stores of no more than MXLEN bits defined in the F, D, and
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* Q extensions.
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*/
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*/
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if ((get_xl_max(ctx) >= MXL_RV64) && ctx->cfg_ptr->ext_zama16b) {
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if (get_xl_max(ctx) == MXL_RV32) {
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memop |= MO_ATOM_NONE;
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} else if (ctx->cfg_ptr->ext_zama16b) {
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memop |= MO_ATOM_WITHIN16;
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memop |= MO_ATOM_WITHIN16;
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} else {
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memop |= MO_ATOM_IFALIGN;
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}
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}
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decode_save_opc(ctx);
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decode_save_opc(ctx);
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@ -71,8 +77,12 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
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REQUIRE_FPU;
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REQUIRE_FPU;
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REQUIRE_EXT(ctx, RVD);
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REQUIRE_EXT(ctx, RVD);
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if ((get_xl_max(ctx) >= MXL_RV64) && ctx->cfg_ptr->ext_zama16b) {
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if (get_xl_max(ctx) == MXL_RV32) {
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memop |= MO_ATOM_NONE;
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} else if (ctx->cfg_ptr->ext_zama16b) {
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memop |= MO_ATOM_WITHIN16;
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memop |= MO_ATOM_WITHIN16;
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} else {
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memop |= MO_ATOM_IFALIGN;
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}
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}
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decode_save_opc(ctx);
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decode_save_opc(ctx);
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